Matthias Weisser wrote:
> Signed-off-by: Matthias Weisser <matthias.weis...@graf-syteco.de>
> ---
> MAINTAINERS | 4 +
> MAKEALL | 1 +
<snip>
> index ed6156f..98c147d 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -2874,6 +2874,13 @@ TNY_A9260_config : unconfig
> @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
> @$(MKCONFIG) -a tny_a9260 arm arm926ejs tny_a9260 calao at91
>
> +#########################################################################
> +## ARM926EJ-S Systems
> +#########################################################################
> +
Change to 'Syteco ARM926EJ-S Systems'
> +jadecpu_config : unconfig
> + @$(MKCONFIG) $(@:_config=) arm arm926ejs jadecpu syteco jade
> +
> ########################################################################
> ## ARM Integrator boards - see doc/README-integrator for more info.
> integratorap_config \
<snip>
> + */
> +
> +#include <common.h>
> +#include <netdev.h>
> +#include <asm/io.h>
> +#include <asm/arch/jade.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#if defined(CONFIG_SHOW_BOOT_PROGRESS)
> +void show_boot_progress(int progress)
> +{
> + printf("Boot reached stage %d\n", progress);
> +}
> +#endif
> +
> +/*
> + * Miscellaneous platform dependent initialisations
> + */
> +int board_init(void)
> +{
board_init should fill out entries in
struct global_data.
See other board like lopgicpd/zoom1 as an example.
Make sure to include the machine id.
> + struct jade_ccnt * ccnt = (struct jade_ccnt *)JADE_CCNT_PHYS_BASE;
> +
> + /* We select mode 0 for group 2 and mode 1 for group 4 */
> + writel(0x00000010, &ccnt->cmux_md);
> +
> + gd->flags = 0;
> +
> + icache_enable();
> +
> + return 0;
> +}
> +
> +int board_late_init(void)
> +{
> + struct jade_gpio *gpio = (struct jade_gpio *)JADE_GPIO_PHYS_BASE;
> + struct jade_pwm *pwm;
> + uint32_t in_word;
> + const char *e;
> + const char *s;
> +
> + /* Check if we have valid display settings and turn on power if so*/
ws
Add as space between 'so*'
> + /* Display 0 */
This should be conditional included if the video in included
#ifdef CONFIG_VIDEO_JADEGDC ..
> + if (getenv("gs_dsp_0_param")) {
> + writel(readl(&gpio->gpdr2) | (1 << 3), &gpio->gpdr2);
> +
> + e = getenv("gs_dsp_0_pwm");
> + if (e != NULL) {
> + uint32_t freq, init;
> +
> + freq = 0;
> + init = 0;
> +
> + s = strchr(e, 'f');
> + if (s != NULL)
> + freq = simple_strtol(s + 2, NULL, 0);
> +
> + s = strchr(e, 'i');
> + if (s != NULL)
> + init = simple_strtol(s + 2, NULL, 0);
> +
> + if (freq > 0) {
> + pwm = (struct jade_pwm *)JADE_PWM0_PHYS_BASE;
> +
> + writel(CONFIG_JADE_IOCLK / 1000 / freq,
> + &pwm->bcr);
> + writel(1002, &pwm->tpr);
> + writel(1, &pwm->pr);
> + writel(init * 10 + 1, &pwm->dr);
> + writel(1, &pwm->cr);
> + writel(1, &pwm->sr);
> + }
> + }
> + }
The video patch has logic to fall back reading
if (penv == NULL) {
penv = getenv("videomode");
if ((i == 1) || (penv == NULL))
Should similar logic be added here ?
> + writel(readl(&gpio->gpddr2) | (1 << 3), &gpio->gpddr2);
> +
> + /* Display 1 */
> + if (getenv("gs_dsp_1_param")) {
> + writel(readl(&gpio->gpdr2) | (1 << 4), &gpio->gpdr2);
> +
> + e = getenv("gs_dsp_1_pwm");
> + if (e != NULL) {
> + uint32_t freq, init;
> +
> + freq = 0;
> + init = 0;
> +
> + s = strchr(e, 'f');
> + if (s != NULL)
> + freq = simple_strtol(s + 2, NULL, 0);
> +
> + s = strchr(e, 'i');
> + if (s != NULL)
> + init = simple_strtol(s + 2, NULL, 0);
> +
> + if (freq > 0) {
> + pwm = (struct jade_pwm *)JADE_PWM1_PHYS_BASE;
> +
> + writel(CONFIG_JADE_IOCLK / 1000 / freq,
> + &pwm->bcr);
> + writel(1002, &pwm->tpr);
> + writel(1, &pwm->pr);
> + writel(init * 10 + 1, &pwm->dr);
> + writel(1, &pwm->cr);
> + writel(1, &pwm->sr);
> + }
> + }
> + }
> + writel(readl(&gpio->gpddr2) | (1 << 4), &gpio->gpddr2);
> +
> + /* 5V enable */
> + writel(readl(&gpio->gpddr1) | (1 << 5), &gpio->gpddr1);
> + writel(readl(&gpio->gpdr1) & ~(1 << 5), &gpio->gpdr1);
> +
> + /* We have special boot options if told by GPIOs */
> + in_word = readl(&gpio->gpdr1);
> +
> + if ((in_word & 0xC0) == 0xC0) {
> + setenv("stdin", "eserial0");
> + setenv("stdout", "eserial0");
> + setenv("stderr", "eserial0");
> + setenv("bootdelay", "10");
> + } else if ((in_word & 0xC0) != 0) {
> + setenv("stdout", "vga");
> + setenv("bootcmd", "mw.l 0x40000000 0 1024; usb start;"
> + "fatls usb 0; fatload usb 0 0x40000000 mcq5resq.bin;"
> + "bootelf 0x40000000; bootelf 0x10080000");
> + setenv("bootdelay", "5");
> + } else{
ws
space between 'else{'
> + setenv("stdin", "serial");
> + setenv("stdout", "serial");
> + setenv("stderr", "serial");
> + if (getenv("gs_devel"))
> + setenv("bootdelay", "5");
> + else
> + setenv("bootdelay", "0");
> + }
> +
> + return 0;
> +}
> +
> +int misc_init_r(void)
> +{
> + setenv("verify", "n");
This should be added to the list of
#define CONFIG_EXTRA_ENV_SETTINGS
set the the board config file.
> + return 0;
> +}
> +
> +/*
> + * DRAM configuration
> + */
> +int dram_init(void)
> +{
> + gd->bd->bi_dram[0].start = PHYS_SDRAM;
> + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
> +
> + return 0;
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> + int rc = 0;
> +#ifdef CONFIG_SMC911X
> + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
> +#endif
> + return rc;
> +}
> +
> diff --git a/board/syteco/jadecpu/lowlevel_init.S
> b/board/syteco/jadecpu/lowlevel_init.S
> new file mode 100644
> index 0000000..73550c9
> --- /dev/null
> +++ b/board/syteco/jadecpu/lowlevel_init.S
> @@ -0,0 +1,279 @@
> +/*
> + * Board specific setup info
> + *
> + * (C) Copyright 2007, mycable GmbH
> + * Carsten Schneider <c...@mycable.de>, Alexander Bigga <a...@mycable.de>
> + *
> + * (C) Copyright 2007, mycable GmbH
> + * Carsten Schneider <c...@mycable.de>, Alexander Bigga <a...@mycable.de>
> + *
> + * (C) Copyright 2003, ARM Ltd.
> + * Philippe Robin, <philippe.ro...@arm.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software/* you can redistribute it and/or
ws
remove '/*'
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation/* either version 2 of
ws
remove '/*'
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY/* without even the implied warranty of
ws
remove '/*'
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program/* if not, write to the Free Software
here too..
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <config.h>
> +#include <version.h>
> +#include <asm/macro.h>
> +#include <asm/arch/jade.h>
> +
> +/* Set up the platform, once the cpu has been initialized */
> +.globl lowlevel_init
> +lowlevel_init:
> +/*
> + * Initialize Clock Reset Generator (CRG)
> + */
> +
> + ldr r0, =JADE_CRG_PHYS_BASE
> +
> + /* Not change the initial value that is set by external pin.*/
> +1: ldr r2, [r0, #CRG_CRPR] /* Wait for PLLREADY */
Use a better label that '1:'
> + tst r2, #0x00000100
> + beq 1b
> +
> + /* Set clock gate control */
> + ldr r1, =0x0000ffff /* Open */
> + str r1, [r0, #CRG_CRHA] /* CRHA: AHB clock */
> + ldr r1, =0x0000ffff /* Open */
> + str r1, [r0, #CRG_CRPA] /* CRPA: APB-A clock */
> + ldr r1, =0xfffffffe /* Close */
> + str r1, [r0, #CRG_CRPB] /* CRPA: APB-B clock */
> + ldr r1, =0x0000ffff /* Open */
> + str r1, [r0, #CRG_CRHB] /* CRHB: ExtAHB clock */
> + ldr r1, =0xffffffef /* Open ARM926EJ-S only */
> + str r1, [r0, #CRG_CRAM] /* CRAM: ARM core clock */
> +
> +/*
> + * Initialize External Bus Interface
> + */
> +
> + ldr r0, =JADE_MEMC_PHYS_BASE
> +
> + /*
> + * SRAM/flash _mode_ registers (XCS4 is set by external pin)
> + * XCS0: Ethernet Controller
> + * XCS2: not used (?)
> + * XCS4: Flash
> + */
> + ldr r1, =0x00000001 /* XCS0: 16bit */
> + str r1, [r0, #0x00]
> + ldr r1, =0x00000001 /* XCS2: 16bit */
> + str r1, [r0, #0x08]
> + ldr r1, =0x00000021 /* XCS4: 16bit, */
> + str r1, [r0, #0x10]
> +
> + /* SRAM/flash _timing_ registers (HCLK=83.3/80MHz) */
> + ldr r1, =0x03061008 /* XCS0: FPGA*/
> + str r1, [r0, #0x20]
> + ldr r1, =0x03061008 /* XCS2: Ethernet */
> + str r1, [r0, #0x28]
> + ldr r1, =0x03061804 /* XCS4: FLASH ROM */
> + str r1, [r0, #0x30]
> +
> + /* SRAM/flash _area_ registers (address of XCS4 is set by hardware) */
> + ldr r1, =0x000000c0 /* XCS0: 0x0c000000/1MB */
> + str r1, [r0, #0x40]
> + ldr r1, =0x00000020 /* XCS2: 0x02000000/1MB */
> + str r1, [r0, #0x48]
> + ldr r1, =0x001f0000 /* XCS4: 32 MB */
> + str r1, [r0, #0x50]
> +
> +/*
> + * Initialize DDR2 Controller
> + */
> +
> + /* Wait for PLL LOCK up time or more */
> + wait_timer 20
> +
> + /*
> + * (2) Initialize DDRIF
> + */
> + ldr r0, =JADE_DDR2C_PHYS_BASE
> + ldr r1, =0x5555
> + strh r1, [r0, #DDR2C_DRIMS]
> +
> + /*
> + * (3) Wait for 20MCKPs(120nsec) or more
> + */
> + wait_timer 20
> +
> + /*
> + * (4) IRESET/IUSRRST release
> + /*
This looks like a programming error
/* -> */ ?
> + ldr r0, =JADE_CCNT_PHYS_BASE
> + ldr r1, =0x00000002
> + str r1, [r0, #CCNT_CDCRC]
> +
<snip>
> + ldr r1, =0x0005 /* EMR(1) command */
> + strh r1, [r0, #DDR2C_DRIC1]
> + ldr r1, =0x0380 /* Extended Mode Register 1 set OCD */
> + strh r1, [r0, #DDR2C_DRIC2]
> + ldr r1, =0xc001
> + strh r1, [r0, #DDR2C_DRIC]
> +
> + ldr r1, =0x0005 /* EMR(1) command */
> + strh r1, [r0, #DDR2C_DRIC1]
> + /* ldr r1, =0x0044 */
Do not include commented out code.
Remove or add appropriate if-def
> + ldr r1, =0x0002 /* EMR(1) set reduced strength */
> + strh r1, [r0, #DDR2C_DRIC2]
> + ldr r1, =0xc001
> + strh r1, [r0, #DDR2C_DRIC]
> +
> + ldr r1, =0x0032 /* Set BT, AL, CL, BL */
> + strh r1, [r0, #DDR2C_DRCM]
> +
> + ldr r1, =0x3418 /* Set tRCD, tRAS, tRP, tRC */
> + strh r1, [r0, #DDR2C_DRCST1]
> +
> + /* ldr r1, =0x2e22 */ /* Set tRFC, tRRD, tWR */
Same here..
> + ldr r1, =0x6e32
> + strh r1, [r0, #DDR2C_DRCST2]
> +
> + /* ldr r1, =0x0051 */ /* Set CNTL, REF_CNT*/
and here..
> + ldr r1, =0x0141 /* (changed) */
> + strh r1, [r0, #DDR2C_DRCR]
> +
> + ldr r1, =0x0002 /* Set Address FIFO (8 steps) */
> + strh r1, [r0, #DDR2C_DRCF]
> +
> + ldr r1, =0x0001 /* Enable AXI Cache */
> + strh r1, [r0, #DDR2C_DRASR]
> +
> + /*
> + * (11) ODT setting
> + */
> + ldr r1, =0x0001
> + strh r1, [r0, #DDR2C_DROBS]
> + ldr r1, =0x0103 /* ODT auto adjustment on */
> + strh r1, [r0, #DDR2C_DROABA]
> + ldr r1, =0x003F /* Set ODT to on 50/100 Ohm */
> + strh r1, [r0, #DDR2C_DRIBSODT1]
> +
> + /*
> + * (12) Shift to ODTCONT ON (SDRAM side) and DDR2C usual operation mode
> + */
> + ldr r1, =0x0001
> + strh r1, [r0, #DDR2C_DROS]
> + ldr r1, =0x4000
> + strh r1, [r0, #DDR2C_DRIC]
> +
> + mov pc, lr
> +
> diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h
> new file mode 100644
> index 0000000..5a19abf
> --- /dev/null
> +++ b/include/configs/jadecpu.h
> @@ -0,0 +1,187 @@
> +/*
> + * (C) Copyright 2007-2008
> + * Matthias Weisser <matthias.weis...@graf-syteco.de>
> + *
> + * Configuation settings for the AT91SAM9260EK & AT91SAM9G20EK boards.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#define CONFIG_JADE
The board and cpu defines go first
move the device configs to later
> +#define CONFIG_JADE_IOCLK (41164767)
This is a strange number. please add a comment.
> +#define CONFIG_SYS_HZ (CONFIG_JADE_IOCLK / 16)
> +#define CONFIG_SYS_TIMERBASE 0xfffe0000
> +
> +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
> +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff
> */
> +
> +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
> +#define CONFIG_SETUP_MEMORY_TAGS 1
> +#define CONFIG_INITRD_TAG 1
> +#define BOARD_LATE_INIT 1
> +
> +/*
> + * Hardware drivers
> + */
> +
> +/*
> + * Serial
> + */
> +#define CONFIG_SERIAL_MULTI
> +#define CONFIG_SYS_NS16550
> +#define CONFIG_SYS_NS16550_SERIAL
> +#define CONFIG_SYS_NS16550_REG_SIZE (-4)
> +#define CONFIG_SYS_NS16550_CLK CONFIG_JADE_IOCLK
> +#define CONFIG_SYS_NS16550_COM1 0xfffe1000 /* UART 0 */
> +#define CONFIG_SYS_NS16550_COM2 0xfff50000 /* UART 2 (SP)
> */
> +#define CONFIG_SYS_NS16550_COM3 0xfff51000 /* UART 3 */
> +#define CONFIG_SYS_NS16550_COM4 0xfff43000 /* UART 4 */
> +
> +#define CONFIG_CONS_INDEX 4
> +
> +/*
> + * Ethernet
> + */
> +#define CONFIG_NET_MULTI
> +#define CONFIG_SMC911X
> +#define CONFIG_SMC911X_BASE 0x02000000
> +#define CONFIG_SMC911X_16_BIT
> +
> +/*
> + * Video
This should be conditional on CONFIG_VIDEO_JADEDC
> + */
> +#define CONFIG_VIDEO
> +#define CONFIG_VIDEO_JADEGDC
> +#define CONFIG_SYS_WHITE_ON_BLACK
> +#define CONFIG_CFB_CONSOLE
> +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
> +#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
> +#define CONFIG_VIDEO_LOGO
> +#define CONFIG_SPLASH_SCREEN
> +#define CONFIG_SPLASH_SCREEN_ALIGN
> +#define CONFIG_VIDEO_BMP_LOGO
> +#define CONFIG_VIDEO_BMP_GZIP
> +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (800*480 + 256*4 + 10*1024)
> +#define VIDEO_KBD_INIT_FCT 0
> +#define VIDEO_TSTC_FCT serial_tstc
> +#define VIDEO_GETC_FCT serial_getc
> +
> +/*
> + * BOOTP options
> + */
> +#define CONFIG_BOOTP_BOOTFILESIZE 1
> +#define CONFIG_BOOTP_BOOTPATH 1
> +#define CONFIG_BOOTP_GATEWAY 1
> +#define CONFIG_BOOTP_HOSTNAME 1
> +
> +/*
> + * Command line configuration.
> + */
> +#include <config_cmd_default.h>
> +#undef CONFIG_CMD_BDI
> +#undef CONFIG_CMD_FPGA
> +#undef CONFIG_CMD_IMI
> +#undef CONFIG_CMD_IMLS
> +#undef CONFIG_CMD_LOADS
> +#undef CONFIG_CMD_SOURCE
> +#undef CONFIG_CMD_NFS
> +#undef CONFIG_CMD_XIMG
> +
> +#define CONFIG_CMD_IMI 1
> +#define CONFIG_CMD_ELF 1
> +#define CONFIG_CMD_PING 1
> +#define CONFIG_CMD_DHCP 1
> +#define CONFIG_CMD_BMP 1
> +#define CONFIG_CMD_USB 1
> +#define CONFIG_CMD_FAT 1
> +#define CONFIG_SYS_HUSH_PARSER
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +
> +/* USB */
> +#define CONFIG_USB_OHCI_NEW
> +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0xFFF81000
> +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "jadeusb"
> +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
ws
convert spaces in the last 3 lines to tabs
Tom
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
