Hello Calvin Please find few comments inline.
Regards Poonam > -----Original Message----- > From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Calvin > Johnson > Sent: Monday, October 09, 2017 2:42 PM > To: u-boot@lists.denx.de > Cc: joe.hershber...@ni.com; Anji Jagarlmudi <anji.jagarlm...@nxp.com> > Subject: [U-Boot] [PATCH 7/9] armv8: fsl-lsch2: configure pfe's scfg & dcfg > registers Reword: configure Qos, cacheable...attributes for PFE by programming SCFG and DFCG registers > > Define init_pfe_scfg_dcfg_regs to configure scfg and dcfg registers of pfe. Consider to reword for more explanation Configure "xyz cacheable attributes, via scfg PFE QoS settings configured as .... via scfg dcfg ?? > > Signed-off-by: Calvin Johnson <calvin.john...@nxp.com> > Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com> > --- > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 18 ++++++++++++++++++ > arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 +++ > 2 files changed, 21 insertions(+) > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c > b/arch/arm/cpu/armv8/fsl-layerscape/soc.c > index 5c429d4..c6815f3 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c > @@ -577,6 +577,24 @@ int setup_chip_volt(void) > return 0; > } > > +#ifdef CONFIG_FSL_PFE > +void init_pfe_scfg_dcfg_regs(void) > +{ > + struct ccsr_scfg *scfg = (struct ccsr_scfg > *)CONFIG_SYS_FSL_SCFG_ADDR; > + > + out_be32(&scfg->pfeasbcr, > + in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0); > + out_be32(&scfg->pfebsbcr, > + in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0); > + > + /* CCI-400 QoS settings for PFE */ This is incomplete sentence, we should also tell what settings are being done. > + out_be32(&scfg->wr_qos1, 0x0ff00000); > + out_be32(&scfg->rd_qos1, 0x0ff00000); Avoid hardcoding/magic numbers > + > + out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x524, 0x2000); Should remove hardcoded values , 0x524, 0x2000. 0x524 does not show up in the LS1012A RM (Rev 0). Please check once. Also adding one liner telling what the above settings mean will help . > #endif > + > void fsl_lsch2_early_init_f(void) > { > struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + diff > --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h > b/arch/arm/include/asm/arch-fsl-layerscape/soc.h > index 697f072..08a42b9 100644 > --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h > +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h > @@ -120,6 +120,9 @@ void fsl_lsch2_early_init_f(void); int > setup_chip_volt(void); > /* Setup core vdd in unit mV */ > int board_setup_core_volt(u32 vdd); > +#ifdef CONFIG_FSL_PFE > +void init_pfe_scfg_dcfg_regs(void); > +#endif > #endif > void ddr_enable_0v9_volt(bool en); > > -- > 2.7.4 > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
