From: Bharat Kumar Gogada <bharat.kumar.gog...@xilinx.com>
- Enabling GTR lane-0 to PCIe
- Enabling PCIe node in device tree
Signed-off-by: Bharat Kumar Gogada <bhara...@xilinx.com>
Signed-off-by: Michal Simek <michal.si...@xilinx.com>
---
arch/arm/dts/zynqmp-zcu102-revA.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts
b/arch/arm/dts/zynqmp-zcu102-revA.dts
index fd7d6466711b..df916d0f77d5 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -168,7 +168,7 @@
gtr_sel0 {
gpio-hog;
gpios = <0 0>;
- output-high; /* PCIE = 0, DP = 1 */
+ output-low; /* PCIE = 0, DP = 1 */
line-name = "sel0";
};
gtr_sel1 {
@@ -551,7 +551,7 @@
drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o
};
&pcie {
-/* status = "okay"; */
+ status = "okay";
};
&qspi {
--
1.9.1
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