Fix whitespace style violations in the MPC83xx SPD-SDRAM code.
Signed-off-by: Mario Six <mario....@gdsys.cc>
---
arch/powerpc/cpu/mpc83xx/spd_sdram.c | 134 +++++++++++++++++------------------
1 file changed, 67 insertions(+), 67 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index 21ab0153fc..48814a09f2 100644
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -160,12 +160,13 @@ long int spd_sdram()
/* Read SPD parameters with I2C */
CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET,
- SPD_EEPROM_ADDR_LEN, (uchar *) &spd, sizeof(spd));
+ SPD_EEPROM_ADDR_LEN, (uchar *)&spd, sizeof(spd));
#ifdef SPD_DEBUG
spd_debug(&spd);
#endif
/* Check the memory type */
- if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type !=
SPD_MEMTYPE_DDR2) {
+ if (spd.mem_type != SPD_MEMTYPE_DDR &&
+ spd.mem_type != SPD_MEMTYPE_DDR2) {
debug("DDR: Module mem type is %02X\n", spd.mem_type);
return 0;
}
@@ -185,14 +186,14 @@ long int spd_sdram()
/* Check if the number of row of the module is in the range of DDRC */
if (spd.nrow_addr < 12 || spd.nrow_addr > 15) {
printf("DDR: Row number is out of range of DDRC, row=%02X\n",
- spd.nrow_addr);
+ spd.nrow_addr);
return 0;
}
/* Check if the number of col of the module is in the range of DDRC */
if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
printf("DDR: Col number is out of range of DDRC, col=%02X\n",
- spd.ncol_addr);
+ spd.ncol_addr);
return 0;
}
@@ -223,22 +224,22 @@ long int spd_sdram()
| (odt_wr_cfg << 16)
| ((spd.nbanks == 8 ? 1 : 0) << 14)
| ((spd.nrow_addr - 12) << 8)
- | (spd.ncol_addr - 8) );
+ | (spd.ncol_addr - 8));
debug("\n");
- debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
- debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
+ debug("cs0_bnds = 0x%08x\n", ddr->csbnds[0].csbnds);
+ debug("cs0_config = 0x%08x\n", ddr->cs_config[0]);
if (n_ranks == 2) {
- ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
- | ((banksize(spd.row_dens) >> 23) - 1) );
ddr->cs_config[1] = ( 1<<31
+ ddr->csbnds[1].csbnds = ((banksize(spd.row_dens) >> 8)
+ | ((banksize(spd.row_dens) >> 23) - 1));
| (odt_rd_cfg << 20)
| (odt_wr_cfg << 16)
| ((spd.nbanks == 8 ? 1 : 0) << 14)
| ((spd.nrow_addr - 12) << 8)
- | (spd.ncol_addr - 8) );
- debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
- debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
+ | (spd.ncol_addr - 8));
+ debug("cs1_bnds = 0x%08x\n", ddr->csbnds[1].csbnds);
+ debug("cs1_config = 0x%08x\n", ddr->cs_config[1]);
}
#else
@@ -248,22 +249,22 @@ long int spd_sdram()
| (odt_wr_cfg << 16)
| ((spd.nbanks == 8 ? 1 : 0) << 14)
| ((spd.nrow_addr - 12) << 8)
- | (spd.ncol_addr - 8) );
+ | (spd.ncol_addr - 8));
debug("\n");
- debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
- debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
+ debug("cs2_bnds = 0x%08x\n", ddr->csbnds[2].csbnds);
+ debug("cs2_config = 0x%08x\n", ddr->cs_config[2]);
if (n_ranks == 2) {
- ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
- | ((banksize(spd.row_dens) >> 23) - 1) );
ddr->cs_config[3] = ( 1<<31
+ ddr->csbnds[3].csbnds = ((banksize(spd.row_dens) >> 8)
+ | ((banksize(spd.row_dens) >> 23) - 1));
| (odt_rd_cfg << 20)
| (odt_wr_cfg << 16)
| ((spd.nbanks == 8 ? 1 : 0) << 14)
| ((spd.nrow_addr - 12) << 8)
- | (spd.ncol_addr - 8) );
- debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
- debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
+ | (spd.ncol_addr - 8));
+ debug("cs3_bnds = 0x%08x\n", ddr->csbnds[3].csbnds);
+ debug("cs3_config = 0x%08x\n", ddr->cs_config[3]);
}
#endif
@@ -304,19 +305,19 @@ long int spd_sdram()
* 5.0 5 1001
*/
caslat = __ilog2(spd.cas_lat);
- if ((spd.mem_type == SPD_MEMTYPE_DDR)
- && (caslat > 6)) {
+ if (spd.mem_type == SPD_MEMTYPE_DDR &&
+ caslat > 6) {
printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
return 0;
- } else if (spd.mem_type == SPD_MEMTYPE_DDR2
- && (caslat < 2 || caslat > 5)) {
+ } else if (spd.mem_type == SPD_MEMTYPE_DDR2 &&
+ (caslat < 2 || caslat > 5)) {
printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
spd.cas_lat);
return 0;
}
debug("DDR: caslat SPD bit is %d\n", caslat);
- max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
+ max_bus_clk = 1000 * 10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
+ (spd.clk_cycle & 0x0f));
max_data_rate = max_bus_clk * 2;
@@ -332,7 +333,7 @@ long int spd_sdram()
caslat = 4;
if (ddrc_clk <= 460 && ddrc_clk > 350)
effective_data_rate = 400;
- else if (ddrc_clk <=350 && ddrc_clk > 280)
+ else if (ddrc_clk <= 350 && ddrc_clk > 280)
effective_data_rate = 333;
else if (ddrc_clk <= 280 && ddrc_clk > 230)
effective_data_rate = 266;
@@ -395,7 +396,7 @@ long int spd_sdram()
if (ddrc_clk <= 350 && ddrc_clk > 280) {
/* DDR controller clk at 280~350 */
printf("DDR: DDR controller freq is more than "
- "max data rate of the module\n");
+ "max data rate of the module\n");
return 0;
} else if (ddrc_clk <= 280 && ddrc_clk > 230) {
/* DDR controller clk at 230~280 */
@@ -411,7 +412,7 @@ long int spd_sdram()
if (ddrc_clk <= 350 && ddrc_clk > 230) {
/* DDR controller clk at 230~350 */
printf("DDR: DDR controller freq is more than "
- "max data rate of the module\n");
+ "max data rate of the module\n");
return 0;
} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
/* DDR controller clk at 90~230 */
@@ -427,7 +428,7 @@ long int spd_sdram()
* Errata DDR6 work around: input enable 2 cycles earlier.
* including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
*/
- if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
+ if (PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR) {
if (caslat == 2)
ddr->debug_reg = 0x201c0000; /* CL=2 */
else if (caslat == 3)
@@ -528,11 +529,11 @@ long int spd_sdram()
trfc_low = (trfc_clk - 8) & 0xf;
ddr->timing_cfg_1 =
- (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */
- ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
- (trcd_clk << 20 ) | /* ACTTORW */
- (caslat_ctrl << 16 ) | /* CASLAT */
- (trfc_low << 12 ) | /* REFEC */
+ (((picos_to_clk(spd.trp * 250) & 0x07) << 28) | /* PRETOACT */
+ ((picos_to_clk(spd.tras * 1000) & 0x0f) << 24) | /* ACTTOPRE */
+ (trcd_clk << 20) | /* ACTTORW */
+ (caslat_ctrl << 16) | /* CASLAT */
+ (trfc_low << 12) | /* REFEC */
((twr_clk & 0x07) << 8) | /* WRRREC */
((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | /* ACTTOACT */
((twtr_clk & 0x07) << 0) /* WRTORD */
@@ -704,33 +705,33 @@ long int spd_sdram()
debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2);
switch (spd.refresh) {
- case 0x00:
- case 0x80:
- refresh_clk = picos_to_clk(15625000);
- break;
- case 0x01:
- case 0x81:
- refresh_clk = picos_to_clk(3900000);
- break;
- case 0x02:
- case 0x82:
- refresh_clk = picos_to_clk(7800000);
- break;
- case 0x03:
- case 0x83:
- refresh_clk = picos_to_clk(31300000);
- break;
- case 0x04:
- case 0x84:
- refresh_clk = picos_to_clk(62500000);
- break;
- case 0x05:
- case 0x85:
- refresh_clk = picos_to_clk(125000000);
- break;
- default:
- refresh_clk = 0x512;
- break;
+ case 0x00:
+ case 0x80:
+ refresh_clk = picos_to_clk(15625000);
+ break;
+ case 0x01:
+ case 0x81:
+ refresh_clk = picos_to_clk(3900000);
+ break;
+ case 0x02:
+ case 0x82:
+ refresh_clk = picos_to_clk(7800000);
+ break;
+ case 0x03:
+ case 0x83:
+ refresh_clk = picos_to_clk(31300000);
+ break;
+ case 0x04:
+ case 0x84:
+ refresh_clk = picos_to_clk(62500000);
+ break;
+ case 0x05:
+ case 0x85:
+ refresh_clk = picos_to_clk(125000000);
+ break;
+ default:
+ refresh_clk = 0x512;
+ break;
}
/*
@@ -823,7 +824,7 @@ long int spd_sdram()
debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
#endif
- debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
+ debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON" : "OFF");
#if defined(CONFIG_DDR_2T_TIMING)
/*
@@ -866,7 +867,7 @@ static __inline__ unsigned long get_tbms (void)
tmp = (unsigned long long)(tbu1);
tmp = (tmp << 32);
tmp += (unsigned long long)(tbl);
- ms = tmp/(tbclk/1000);
+ ms = tmp / (tbclk / 1000);
return ms;
}
@@ -877,7 +878,7 @@ static __inline__ unsigned long get_tbms (void)
void ddr_enable_ecc(unsigned int dram_size)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile ddr83xx_t *ddr= &immap->ddr;
+ volatile ddr83xx_t *ddr = &immap->ddr;
unsigned long t_start, t_end;
register u64 *p;
register uint size;
@@ -893,9 +894,8 @@ void ddr_enable_ecc(unsigned int dram_size)
#else
debug("ddr init: CPU FP write method\n");
size = dram_size;
- for (p = 0; p < (u64*)(size); p++) {
- ppcDWstore((u32*)p, pattern);
- }
+ for (p = 0; p < (u64 *)(size); p++)
+ ppcDWstore((u32 *)p, pattern);
__asm__ __volatile__ ("sync");
#endif
--
2.11.0
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