Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values.

Program register USB_PHY_RX_OVRD_IN_HI in certain sequence
to make the Rx compliance test pass.

Signed-off-by: Ran Wang <ran.wan...@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 +
 arch/arm/cpu/armv8/fsl-layerscape/soc.c   | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 3518d8601d..85b7c70937 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -72,6 +72,7 @@ config ARCH_LS1088A
        select SYS_FSL_ERRATUM_A010165
        select SYS_FSL_ERRATUM_A008511
        select SYS_FSL_ERRATUM_A008850
+       select SYS_FSL_ERRATUM_A009007
        select SYS_FSL_HAS_CCI400
        select SYS_FSL_HAS_DDR4
        select SYS_FSL_HAS_RGMII
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 6698c0467d..53620ebf19 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -127,7 +127,7 @@ static void erratum_a008997(void)
        out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);      
\
        out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
 
-#elif defined(CONFIG_ARCH_LS2080A)
+#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
 
 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy)     \
        out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
@@ -149,7 +149,7 @@ static void erratum_a009007(void)
 
        usb_phy = (void __iomem *)SCFG_USB_PHY3;
        PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
-#elif defined(CONFIG_ARCH_LS2080A)
+#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
        void __iomem *dcsr = (void __iomem *)DCSR_BASE;
 
        PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
-- 
2.14.1

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