Cleans up the s3c24x0 header files by changing the upper case members
of the s3c24x0 register structures to lower case and changing all code
that uses these register structures.
Signed-off-by: Kevin Morfitt <kevin.morf...@fearnside-systems.co.uk>
---
The patches are based on the u-boot-samsung repository.
checkpatch reports no errors. 'MAKEALL ARM9' reports no new build
errors or warnings.
cpu/arm920t/s3c24x0/interrupts.c | 2 +-
cpu/arm920t/s3c24x0/speed.c | 8 +-
cpu/arm920t/s3c24x0/timer.c | 24 +-
cpu/arm920t/s3c24x0/usb.c | 16 +-
cpu/arm920t/s3c24x0/usb_ohci.c | 112 +++---
cpu/arm920t/s3c24x0/usb_ohci.h | 16 +-
drivers/i2c/s3c24x0_i2c.c | 166 +++++-----
drivers/mtd/nand/s3c2410_nand.c | 18 +-
drivers/rtc/s3c24x0_rtc.c | 62 ++--
drivers/serial/serial_s3c24x0.c | 26 +-
include/asm-arm/arch-s3c24x0/s3c24x0.h | 624 ++++++++++++++++----------------
11 files changed, 538 insertions(+), 536 deletions(-)
diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/interrupts.c
index 879fda6..9556a5f 100644
--- a/cpu/arm920t/s3c24x0/interrupts.c
+++ b/cpu/arm920t/s3c24x0/interrupts.c
@@ -37,6 +37,6 @@
void do_irq (struct pt_regs *pt_regs)
{
struct s3c24x0_interrupt *irq = s3c24x0_get_base_interrupt();
- u_int32_t intpnd = readl(&irq->INTPND);
+ u_int32_t intpnd = readl(&irq->intpnd);
}
diff --git a/cpu/arm920t/s3c24x0/speed.c b/cpu/arm920t/s3c24x0/speed.c
index b13283a..58e8865 100644
--- a/cpu/arm920t/s3c24x0/speed.c
+++ b/cpu/arm920t/s3c24x0/speed.c
@@ -54,9 +54,9 @@ static ulong get_PLLCLK(int pllreg)
ulong r, m, p, s;
if (pllreg == MPLL)
- r = readl(&clk_power->MPLLCON);
+ r = readl(&clk_power->mpllcon);
else if (pllreg == UPLL)
- r = readl(&clk_power->UPLLCON);
+ r = readl(&clk_power->upllcon);
else
hang();
@@ -78,7 +78,7 @@ ulong get_HCLK(void)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
- return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK();
+ return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK();
}
/* return PCLK frequency */
@@ -86,7 +86,7 @@ ulong get_PCLK(void)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
- return (readl(&clk_power->CLKDIVN) & 1) ? get_HCLK() / 2 : get_HCLK();
+ return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK();
}
/* return UCLK frequency */
diff --git a/cpu/arm920t/s3c24x0/timer.c b/cpu/arm920t/s3c24x0/timer.c
index cd06f6b..a0e2a38 100644
--- a/cpu/arm920t/s3c24x0/timer.c
+++ b/cpu/arm920t/s3c24x0/timer.c
@@ -39,11 +39,11 @@ int timer_load_val = 0;
static ulong timer_clk;
/* macro to read the 16 bit timer */
-static inline ulong READ_TIMER(void)
+static inline ulong read_timer(void)
{
struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
- return readl(&timers->TCNTO4) & 0xffff;
+ return readl(&timers->tcnto4) & 0xffff;
}
static ulong timestamp;
@@ -56,7 +56,7 @@ int timer_init(void)
/* use PWM Timer 4 because it has no output */
/* prescaler for Timer 4 is 16 */
- writel(0x0f00, &timers->TCFG0);
+ writel(0x0f00, &timers->tcfg0);
if (timer_load_val == 0) {
/*
* for 10 ms clock period @ PCLK with 4 bit divider = 1/2
@@ -68,13 +68,13 @@ int timer_init(void)
}
/* load value for 10 ms timeout */
lastdec = timer_load_val;
- writel(timer_load_val, &timers->TCNTB4);
+ writel(timer_load_val, &timers->tcntb4);
/* auto load, manual update of Timer 4 */
- tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000;
- writel(tmr, &timers->TCON);
+ tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
+ writel(tmr, &timers->tcon);
/* auto load, start Timer 4 */
tmr = (tmr & ~0x0700000) | 0x0500000;
- writel(tmr, &timers->TCON);
+ writel(tmr, &timers->tcon);
timestamp = 0;
return (0);
@@ -115,7 +115,7 @@ void udelay(unsigned long usec)
void reset_timer_masked(void)
{
/* reset time */
- lastdec = READ_TIMER();
+ lastdec = read_timer();
timestamp = 0;
}
@@ -155,7 +155,7 @@ void udelay_masked(unsigned long usec)
*/
unsigned long long get_ticks(void)
{
- ulong now = READ_TIMER();
+ ulong now = read_timer();
if (lastdec >= now) {
/* normal mode */
@@ -204,13 +204,13 @@ void reset_cpu(ulong ignored)
watchdog = s3c24x0_get_base_watchdog();
/* Disable watchdog */
- writel(0x0000, &watchdog->WTCON);
+ writel(0x0000, &watchdog->wtcon);
/* Initialize watchdog timer count register */
- writel(0x0001, &watchdog->WTCNT);
+ writel(0x0001, &watchdog->wtcnt);
/* Enable watchdog timer; assert reset at timer timeout */
- writel(0x0021, &watchdog->WTCON);
+ writel(0x0021, &watchdog->wtcon);
while (1)
/* loop forever and wait for reset to happen */;
diff --git a/cpu/arm920t/s3c24x0/usb.c b/cpu/arm920t/s3c24x0/usb.c
index e468ed0..3d51321 100644
--- a/cpu/arm920t/s3c24x0/usb.c
+++ b/cpu/arm920t/s3c24x0/usb.c
@@ -39,30 +39,32 @@ int usb_cpu_init(void)
* Set the 48 MHz UPLL clocking. Values are taken from
* "PLL value selection guide", 6-23, s3c2400_UM.pdf.
*/
- writel((40 << 12) + (1 << 4) + 2, &clk_power->UPLLCON);
+ writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon);
/* 1 = use pads related USB for USB host */
- writel(readl(&gpio->MISCCR) | 0x8, &gpio->MISCCR);
+ writel(readl(&gpio->misccr) | 0x8, &gpio->misccr);
/*
* Enable USB host clock.
*/
- writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
+ writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
return 0;
}
int usb_cpu_stop(void)
{
- struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+ struct s3c24x0_clock_power *clk_power =
+ s3c24x0_get_base_clock_power();
/* may not want to do this */
- writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
+ writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
return 0;
}
int usb_cpu_init_fail(void)
{
- struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
- writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
+ struct s3c24x0_clock_power *clk_power =
+ s3c24x0_get_base_clock_power();
+ writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
return 0;
}
diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c
index 5aa8d64..5f999e0 100644
--- a/cpu/arm920t/s3c24x0/usb_ohci.c
+++ b/cpu/arm920t/s3c24x0/usb_ohci.c
@@ -212,8 +212,8 @@ void ep_print_int_eds(struct ohci *ohci, char *str)
printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i);
while (*ed_p != 0 && j--) {
struct ed *ed = (struct ed *) m32_swap(ed_p);
- printf(" ed: %4x;", ed->hwINFO);
- ed_p = &ed->hwNextED;
+ printf(" ed: %4x;", ed->hwinfo);
+ ed_p = &ed->hwnexted;
}
printf("\n");
}
@@ -241,10 +241,10 @@ static void maybe_print_eds(char *label, __u32 value)
if (value) {
dbg("%s %08x", label, value);
- dbg("%08x", edp->hwINFO);
- dbg("%08x", edp->hwTailP);
- dbg("%08x", edp->hwHeadP);
- dbg("%08x", edp->hwNextED);
+ dbg("%08x", edp->hwinfo);
+ dbg("%08x", edp->hwtailp);
+ dbg("%08x", edp->hwheadp);
+ dbg("%08x", edp->hwnexted);
}
}
@@ -490,11 +490,11 @@ static int ep_link(struct ohci *ohci, struct ed *edi)
switch (ed->type) {
case PIPE_CONTROL:
- ed->hwNextED = 0;
+ ed->hwnexted = 0;
if (ohci->ed_controltail == NULL) {
writel((u32)ed, &ohci->regs->ed_controlhead);
} else {
- ohci->ed_controltail->hwNextED = (__u32) m32_swap(ed);
+ ohci->ed_controltail->hwnexted = (__u32) m32_swap(ed);
}
ed->ed_prev = ohci->ed_controltail;
if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
@@ -506,11 +506,11 @@ static int ep_link(struct ohci *ohci, struct ed *edi)
break;
case PIPE_BULK:
- ed->hwNextED = 0;
+ ed->hwnexted = 0;
if (ohci->ed_bulktail == NULL) {
writel((u32)ed, &ohci->regs->ed_bulkhead);
} else {
- ohci->ed_bulktail->hwNextED = (__u32) m32_swap(ed);
+ ohci->ed_bulktail->hwnexted = (__u32) m32_swap(ed);
}
ed->ed_prev = ohci->ed_bulktail;
if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
@@ -534,43 +534,43 @@ static int ep_link(struct ohci *ohci, struct ed *edi)
static int ep_unlink(struct ohci *ohci, struct ed *ed)
{
struct ed *next;
- ed->hwINFO |= m32_swap(OHCI_ED_SKIP);
+ ed->hwinfo |= m32_swap(OHCI_ED_SKIP);
switch (ed->type) {
case PIPE_CONTROL:
if (ed->ed_prev == NULL) {
- if (!ed->hwNextED) {
+ if (!ed->hwnexted) {
ohci->hc_control &= ~OHCI_CTRL_CLE;
writel(ohci->hc_control, &ohci->regs->control);
}
- writel(m32_swap(*((__u32 *) &ed->hwNextED)),
+ writel(m32_swap(*((__u32 *) &ed->hwnexted)),
&ohci->regs->ed_controlhead);
} else {
- ed->ed_prev->hwNextED = ed->hwNextED;
+ ed->ed_prev->hwnexted = ed->hwnexted;
}
if (ohci->ed_controltail == ed) {
ohci->ed_controltail = ed->ed_prev;
} else {
- next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED));
+ next = (struct ed *)m32_swap(*((__u32 *)&ed->hwnexted));
next->ed_prev = ed->ed_prev;
}
break;
case PIPE_BULK:
if (ed->ed_prev == NULL) {
- if (!ed->hwNextED) {
+ if (!ed->hwnexted) {
ohci->hc_control &= ~OHCI_CTRL_BLE;
writel(ohci->hc_control, &ohci->regs->control);
}
- writel(m32_swap(*((__u32 *) &ed->hwNextED)),
+ writel(m32_swap(*((__u32 *) &ed->hwnexted)),
&ohci->regs->ed_bulkhead);
} else {
- ed->ed_prev->hwNextED = ed->hwNextED;
+ ed->ed_prev->hwnexted = ed->hwnexted;
}
if (ohci->ed_bulktail == ed) {
ohci->ed_bulktail = ed->ed_prev;
} else {
- next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED));
+ next = (struct ed *)m32_swap(*((__u32 *)&ed->hwnexted));
next->ed_prev = ed->ed_prev;
}
break;
@@ -605,17 +605,17 @@ static struct ed *ep_add_ed(struct usb_device *usb_dev,
unsigned long pipe)
}
if (ed->state == ED_NEW) {
- ed->hwINFO = m32_swap(OHCI_ED_SKIP); /* skip ed */
+ ed->hwinfo = m32_swap(OHCI_ED_SKIP); /* skip ed */
/* dummy td; end of td list for ed */
td = td_alloc(usb_dev);
- ed->hwTailP = (__u32) m32_swap(td);
- ed->hwHeadP = ed->hwTailP;
+ ed->hwtailp = (__u32) m32_swap(td);
+ ed->hwheadp = ed->hwtailp;
ed->state = ED_UNLINK;
ed->type = usb_pipetype(pipe);
ohci_dev.ed_cnt++;
}
- ed->hwINFO = m32_swap(usb_pipedevice(pipe)
+ ed->hwinfo = m32_swap(usb_pipedevice(pipe)
| usb_pipeendpoint(pipe) << 7
| (usb_pipeisoc(pipe) ? 0x8000 : 0)
| (usb_pipecontrol(pipe) ? 0 :
@@ -647,11 +647,11 @@ static void td_fill(struct ohci *ohci, unsigned int info,
void *data, int len,
}
/* use this td as the next dummy */
td_pt = urb_priv->td[index];
- td_pt->hwNextTD = 0;
+ td_pt->hwnexttd = 0;
/* fill the old dummy TD */
td = urb_priv->td[index] =
- (struct td *) (m32_swap(urb_priv->ed->hwTailP) & ~0xf);
+ (struct td *) (m32_swap(urb_priv->ed->hwtailp) & ~0xf);
td->ed = urb_priv->ed;
td->next_dl_td = NULL;
@@ -668,16 +668,16 @@ static void td_fill(struct ohci *ohci, unsigned int info,
void *data, int len,
if (!len)
data = 0;
- td->hwINFO = (__u32) m32_swap(info);
- td->hwCBP = (__u32) m32_swap(data);
+ td->hwinfo = (__u32) m32_swap(info);
+ td->hwcbp = (__u32) m32_swap(data);
if (data)
- td->hwBE = (__u32) m32_swap(data + len - 1);
+ td->hwbe = (__u32) m32_swap(data + len - 1);
else
- td->hwBE = 0;
- td->hwNextTD = (__u32) m32_swap(td_pt);
+ td->hwbe = 0;
+ td->hwnexttd = (__u32) m32_swap(td_pt);
/* append to queue */
- td->ed->hwTailP = td->hwNextTD;
+ td->ed->hwtailp = td->hwnexttd;
}
/*-------------------------------------------------------------------------*/
@@ -765,20 +765,20 @@ static void td_submit_job(struct usb_device *dev,
unsigned long pipe,
static void dl_transfer_length(struct td *td)
{
- __u32 tdINFO, tdBE, tdCBP;
+ __u32 tdinfo, tdbe, tdcbp;
struct urb_priv *lurb_priv = &urb_priv;
- tdINFO = m32_swap(td->hwINFO);
- tdBE = m32_swap(td->hwBE);
- tdCBP = m32_swap(td->hwCBP);
+ tdinfo = m32_swap(td->hwinfo);
+ tdbe = m32_swap(td->hwbe);
+ tdcbp = m32_swap(td->hwcbp);
if (!(usb_pipecontrol(lurb_priv->pipe) &&
((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
- if (tdBE != 0) {
- if (td->hwCBP == 0)
- lurb_priv->actual_length += tdBE - td->data + 1;
+ if (tdbe != 0) {
+ if (td->hwcbp == 0)
+ lurb_priv->actual_length += tdbe - td->data + 1;
else
- lurb_priv->actual_length += tdCBP - td->data;
+ lurb_priv->actual_length += tdcbp - td->data;
}
}
}
@@ -802,30 +802,30 @@ static struct td *dl_reverse_done_list(struct ohci *ohci)
while (td_list_hc) {
td_list = (struct td *) td_list_hc;
- if (TD_CC_GET(m32_swap(td_list->hwINFO))) {
+ if (TD_CC_GET(m32_swap(td_list->hwinfo))) {
lurb_priv = &urb_priv;
dbg(" USB-error/status: %x : %p",
- TD_CC_GET(m32_swap(td_list->hwINFO)), td_list);
- if (td_list->ed->hwHeadP & m32_swap(0x1)) {
+ TD_CC_GET(m32_swap(td_list->hwinfo)), td_list);
+ if (td_list->ed->hwheadp & m32_swap(0x1)) {
if (lurb_priv &&
((td_list->index+1) < lurb_priv->length)) {
tmp = lurb_priv->length - 1;
- td_list->ed->hwHeadP =
- (lurb_priv->td[tmp]->hwNextTD &
+ td_list->ed->hwheadp =
+ (lurb_priv->td[tmp]->hwnexttd &
m32_swap(0xfffffff0)) |
- (td_list->ed->hwHeadP &
+ (td_list->ed->hwheadp &
m32_swap(0x2));
lurb_priv->td_cnt += lurb_priv->length -
td_list->index - 1;
} else
- td_list->ed->hwHeadP &=
+ td_list->ed->hwheadp &=
m32_swap(0xfffffff2);
}
}
td_list->next_dl_td = td_rev;
td_rev = td_list;
- td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0;
+ td_list_hc = m32_swap(td_list->hwnexttd) & 0xfffffff0;
}
return td_list;
@@ -848,7 +848,7 @@ static int dl_done_list(struct ohci *ohci, struct td
*td_list)
td_list_next = td_list->next_dl_td;
lurb_priv = &urb_priv;
- tdINFO = m32_swap(td_list->hwINFO);
+ tdINFO = m32_swap(td_list->hwinfo);
ed = td_list->ed;
@@ -874,8 +874,8 @@ static int dl_done_list(struct ohci *ohci, struct td
*td_list)
lurb_priv->td_cnt, lurb_priv->length);
if (ed->state != ED_NEW) {
- edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0;
- edTailP = m32_swap(ed->hwTailP);
+ edHeadP = m32_swap(ed->hwheadp) & 0xfffffff0;
+ edTailP = m32_swap(ed->hwtailp);
/* unlink eds if they are not busy */
if ((edHeadP == edTailP) && (ed->state == ED_OPER))
@@ -1666,13 +1666,13 @@ int usb_lowlevel_init(void)
* Set the 48 MHz UPLL clocking. Values are taken from
* "PLL value selection guide", 6-23, s3c2400_UM.pdf.
*/
- clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
- gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
+ clk_power->upllcon = ((40 << 12) + (1 << 4) + 2);
+ gpio->misccr |= 0x8; /* 1 = use pads related USB for USB host */
/*
* Enable USB host clock.
*/
- clk_power->CLKCON |= (1 << 4);
+ clk_power->clkcon |= (1 << 4);
memset(&gohci, 0, sizeof(struct ohci));
memset(&urb_priv, 0, sizeof(struct urb_priv));
@@ -1709,7 +1709,7 @@ int usb_lowlevel_init(void)
if (hc_reset(&gohci) < 0) {
hc_release_ohci(&gohci);
/* Initialization failed */
- clk_power->CLKCON &= ~(1 << 4);
+ clk_power->clkcon &= ~(1 << 4);
return -1;
}
@@ -1722,7 +1722,7 @@ int usb_lowlevel_init(void)
err("can't start usb-%s", gohci.slot_name);
hc_release_ohci(&gohci);
/* Initialization failed */
- clk_power->CLKCON &= ~(1 << 4);
+ clk_power->clkcon &= ~(1 << 4);
return -1;
}
#ifdef DEBUG
@@ -1748,7 +1748,7 @@ int usb_lowlevel_stop(void)
/* call hc_release_ohci() here ? */
hc_reset(&gohci);
/* may not want to do this */
- clk_power->CLKCON &= ~(1 << 4);
+ clk_power->clkcon &= ~(1 << 4);
return 0;
}
diff --git a/cpu/arm920t/s3c24x0/usb_ohci.h b/cpu/arm920t/s3c24x0/usb_ohci.h
index f272d78..a6cc293 100644
--- a/cpu/arm920t/s3c24x0/usb_ohci.h
+++ b/cpu/arm920t/s3c24x0/usb_ohci.h
@@ -38,10 +38,10 @@ static int cc_to_error[16] = {
/* usb_ohci_ed */
struct ed {
- __u32 hwINFO;
- __u32 hwTailP;
- __u32 hwHeadP;
- __u32 hwNextED;
+ __u32 hwinfo;
+ __u32 hwtailp;
+ __u32 hwheadp;
+ __u32 hwnexted;
struct ed *ed_prev;
__u8 int_period;
@@ -97,10 +97,10 @@ struct ed {
#define MAXPSW 1
struct td {
- __u32 hwINFO;
- __u32 hwCBP; /* Current Buffer Pointer */
- __u32 hwNextTD; /* Next TD Pointer */
- __u32 hwBE; /* Memory Buffer End Pointer */
+ __u32 hwinfo;
+ __u32 hwcbp; /* Current Buffer Pointer */
+ __u32 hwnexttd; /* Next TD Pointer */
+ __u32 hwbe; /* Memory Buffer End Pointer */
__u8 unused;
__u8 index;
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index c8371cf..13508b1 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -53,63 +53,63 @@
#define I2C_TIMEOUT 1 /* 1 second */
-static int GetI2CSDA(void)
+static int get_i2c_sda(void)
{
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
#ifdef CONFIG_S3C2410
- return (readl(&gpio->GPEDAT) & 0x8000) >> 15;
+ return (readl(&gpio->gpedat) & 0x8000) >> 15;
#endif
#ifdef CONFIG_S3C2400
- return (readl(&gpio->PGDAT) & 0x0020) >> 5;
+ return (readl(&gpio->pgdat) & 0x0020) >> 5;
#endif
}
#if 0
-static void SetI2CSDA(int x)
+static void set_i2c_sda(int x)
{
rGPEDAT = (rGPEDAT & ~0x8000) | (x & 1) << 15;
}
#endif
-static void SetI2CSCL(int x)
+static void set_i2c_scl(int x)
{
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
#ifdef CONFIG_S3C2410
- writel((readl(&gpio->GPEDAT) & ~0x4000) | (x & 1) << 14, &gpio->GPEDAT);
+ writel((readl(&gpio->gpedat) & ~0x4000) | (x & 1) << 14, &gpio->gpedat);
#endif
#ifdef CONFIG_S3C2400
- writel((readl(&gpio->PGDAT) & ~0x0040) | (x & 1) << 6, &gpio->PGDAT);
+ writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat);
#endif
}
-static int WaitForXfer(void)
+static int wait_for_xfer(void)
{
struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
int i;
i = I2C_TIMEOUT * 10000;
- while (!(readl(&i2c->IICCON) & I2CCON_IRPND) && (i > 0)) {
+ while (!(readl(&i2c->iiccon) & I2CCON_IRPND) && (i > 0)) {
udelay(100);
i--;
}
- return (readl(&i2c->IICCON) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
+ return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
}
-static int IsACK(void)
+static int is_ack(void)
{
struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
- return !(readl(&i2c->IICSTAT) & I2CSTAT_NACK);
+ return !(readl(&i2c->iicstat) & I2CSTAT_NACK);
}
-static void ReadWriteByte(void)
+static void read_write_byte(void)
{
struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
- writel(readl(&i2c->IICCON) & ~I2CCON_IRPND, &i2c->IICCON);
+ writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
}
void i2c_init(int speed, int slaveadd)
@@ -122,52 +122,52 @@ void i2c_init(int speed, int slaveadd)
/* wait for some time to give previous transfer a chance to finish */
i = I2C_TIMEOUT * 1000;
- while ((readl(&i2c->IICSTAT) && I2CSTAT_BSY) && (i > 0)) {
+ while ((readl(&i2c->iicstat) && I2CSTAT_BSY) && (i > 0)) {
udelay(1000);
i--;
}
- if ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
+ if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || get_i2c_sda() == 0) {
#ifdef CONFIG_S3C2410
- ulong old_gpecon = readl(&gpio->GPECON);
+ ulong old_gpecon = readl(&gpio->gpecon);
#endif
#ifdef CONFIG_S3C2400
- ulong old_gpecon = readl(&gpio->PGCON);
+ ulong old_gpecon = readl(&gpio->pgcon);
#endif
/* bus still busy probably by (most) previously interrupted
transfer */
#ifdef CONFIG_S3C2410
/* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
- writel((readl(&gpio->GPECON) & ~0xF0000000) | 0x10000000,
- &gpio->GPECON);
+ writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000,
+ &gpio->gpecon);
#endif
#ifdef CONFIG_S3C2400
/* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
- writel((readl(&gpio->PGCON) & ~0x00003c00) | 0x00001000,
- &gpio->PGCON);
+ writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000,
+ &gpio->pgcon);
#endif
/* toggle I2CSCL until bus idle */
- SetI2CSCL(0);
+ set_i2c_scl(0);
udelay(1000);
i = 10;
- while ((i > 0) && (GetI2CSDA() != 1)) {
- SetI2CSCL(1);
+ while ((i > 0) && (get_i2c_sda() != 1)) {
+ set_i2c_scl(1);
udelay(1000);
- SetI2CSCL(0);
+ set_i2c_scl(0);
udelay(1000);
i--;
}
- SetI2CSCL(1);
+ set_i2c_scl(1);
udelay(1000);
/* restore pin functions */
#ifdef CONFIG_S3C2410
- writel(old_gpecon, &gpio->GPECON);
+ writel(old_gpecon, &gpio->gpecon);
#endif
#ifdef CONFIG_S3C2400
- writel(old_gpecon, &gpio->PGCON);
+ writel(old_gpecon, &gpio->pgcon);
#endif
}
@@ -183,13 +183,13 @@ void i2c_init(int speed, int slaveadd)
/* set prescaler, divisor according to freq, also set
* ACKGEN, IRQ */
- writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->IICCON);
+ writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
/* init to SLAVE REVEIVE and set slaveaddr */
- writel(0, &i2c->IICSTAT);
- writel(slaveadd, &i2c->IICADD);
+ writel(0, &i2c->iicstat);
+ writel(slaveadd, &i2c->iicadd);
/* program Master Transmit (and implicit STOP) */
- writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT);
+ writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
}
@@ -218,92 +218,92 @@ int i2c_transfer(unsigned char cmd_type,
/* Check I2C bus idle */
i = I2C_TIMEOUT * 1000;
- while ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) && (i > 0)) {
+ while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
udelay(1000);
i--;
}
- if (readl(&i2c->IICSTAT) & I2CSTAT_BSY)
+ if (readl(&i2c->iicstat) & I2CSTAT_BSY)
return I2C_NOK_TOUT;
- writel(readl(&i2c->IICCON) | 0x80, &i2c->IICCON);
+ writel(readl(&i2c->iiccon) | 0x80, &i2c->iiccon);
result = I2C_OK;
switch (cmd_type) {
case I2C_WRITE:
if (addr && addr_len) {
- writel(chip, &i2c->IICDS);
+ writel(chip, &i2c->iicds);
/* send START */
writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
- &i2c->IICSTAT);
+ &i2c->iicstat);
i = 0;
while ((i < addr_len) && (result == I2C_OK)) {
- result = WaitForXfer();
- writel(addr[i], &i2c->IICDS);
- ReadWriteByte();
+ result = wait_for_xfer();
+ writel(addr[i], &i2c->iicds);
+ read_write_byte();
i++;
}
i = 0;
while ((i < data_len) && (result == I2C_OK)) {
- result = WaitForXfer();
- writel(data[i], &i2c->IICDS);
- ReadWriteByte();
+ result = wait_for_xfer();
+ writel(data[i], &i2c->iicds);
+ read_write_byte();
i++;
}
} else {
- writel(chip, &i2c->IICDS);
+ writel(chip, &i2c->iicds);
/* send START */
writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
- &i2c->IICSTAT);
+ &i2c->iicstat);
i = 0;
while ((i < data_len) && (result = I2C_OK)) {
- result = WaitForXfer();
- writel(data[i], &i2c->IICDS);
- ReadWriteByte();
+ result = wait_for_xfer();
+ writel(data[i], &i2c->iicds);
+ read_write_byte();
i++;
}
}
if (result == I2C_OK)
- result = WaitForXfer();
+ result = wait_for_xfer();
/* send STOP */
- writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT);
- ReadWriteByte();
+ writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
+ read_write_byte();
break;
case I2C_READ:
if (addr && addr_len) {
- writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT);
- writel(chip, &i2c->IICDS);
+ writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
+ writel(chip, &i2c->iicds);
/* send START */
- writel(readl(&i2c->IICSTAT) | I2C_START_STOP,
- &i2c->IICSTAT);
- result = WaitForXfer();
- if (IsACK()) {
+ writel(readl(&i2c->iicstat) | I2C_START_STOP,
+ &i2c->iicstat);
+ result = wait_for_xfer();
+ if (is_ack()) {
i = 0;
while ((i < addr_len) && (result == I2C_OK)) {
- writel(addr[i], &i2c->IICDS);
- ReadWriteByte();
- result = WaitForXfer();
+ writel(addr[i], &i2c->iicds);
+ read_write_byte();
+ result = wait_for_xfer();
i++;
}
- writel(chip, &i2c->IICDS);
+ writel(chip, &i2c->iicds);
/* resend START */
writel(I2C_MODE_MR | I2C_TXRX_ENA |
- I2C_START_STOP, &i2c->IICSTAT);
- ReadWriteByte();
- result = WaitForXfer();
+ I2C_START_STOP, &i2c->iicstat);
+ read_write_byte();
+ result = wait_for_xfer();
i = 0;
while ((i < data_len) && (result == I2C_OK)) {
/* disable ACK for final READ */
if (i == data_len - 1)
- writel(readl(&i2c->IICCON)
- & ~0x80, &i2c->IICCON);
- ReadWriteByte();
- result = WaitForXfer();
- data[i] = readl(&i2c->IICDS);
+ writel(readl(&i2c->iiccon)
+ & ~0x80, &i2c->iiccon);
+ read_write_byte();
+ result = wait_for_xfer();
+ data[i] = readl(&i2c->iicds);
i++;
}
} else {
@@ -311,23 +311,23 @@ int i2c_transfer(unsigned char cmd_type,
}
} else {
- writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT);
- writel(chip, &i2c->IICDS);
+ writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
+ writel(chip, &i2c->iicds);
/* send START */
- writel(readl(&i2c->IICSTAT) | I2C_START_STOP,
- &i2c->IICSTAT);
- result = WaitForXfer();
+ writel(readl(&i2c->iicstat) | I2C_START_STOP,
+ &i2c->iicstat);
+ result = wait_for_xfer();
- if (IsACK()) {
+ if (is_ack()) {
i = 0;
while ((i < data_len) && (result == I2C_OK)) {
/* disable ACK for final READ */
if (i == data_len - 1)
- writel(readl(&i2c->IICCON) &
- ~0x80, &i2c->IICCON);
- ReadWriteByte();
- result = WaitForXfer();
- data[i] = readl(&i2c->IICDS);
+ writel(readl(&i2c->iiccon) &
+ ~0x80, &i2c->iiccon);
+ read_write_byte();
+ result = wait_for_xfer();
+ data[i] = readl(&i2c->iicds);
i++;
}
} else {
@@ -336,8 +336,8 @@ int i2c_transfer(unsigned char cmd_type,
}
/* send STOP */
- writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT);
- ReadWriteByte();
+ writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
+ read_write_byte();
break;
default:
diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c
index 3f15d2d..96a2bf0 100644
--- a/drivers/mtd/nand/s3c2410_nand.c
+++ b/drivers/mtd/nand/s3c2410_nand.c
@@ -54,11 +54,11 @@ static void s3c2410_hwcontrol(struct mtd_info *mtd, int
cmd, unsigned int ctrl)
chip->IO_ADDR_W = (void *)IO_ADDR_W;
if (ctrl & NAND_NCE)
- writel(readl(&nand->NFCONF) & ~S3C2410_NFCONF_nFCE,
- &nand->NFCONF);
+ writel(readl(&nand->nfconf) & ~S3C2410_NFCONF_nFCE,
+ &nand->nfconf);
else
- writel(readl(&nand->NFCONF) | S3C2410_NFCONF_nFCE,
- &nand->NFCONF);
+ writel(readl(&nand->nfconf) | S3C2410_NFCONF_nFCE,
+ &nand->nfconf);
}
if (cmd != NAND_CMD_NONE)
@@ -69,7 +69,7 @@ static int s3c2410_dev_ready(struct mtd_info *mtd)
{
struct s3c2410_nand *nand = s3c2410_get_base_nand();
debugX(1, "dev_ready\n");
- return readl(&nand->NFSTAT) & 0x01;
+ return readl(&nand->nfstat) & 0x01;
}
#ifdef CONFIG_S3C2410_NAND_HWECC
@@ -77,7 +77,7 @@ void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
{
struct s3c2410_nand *nand = s3c2410_get_base_nand();
debugX(1, "s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode);
- writel(readl(&nand->NFCONF) | S3C2410_NFCONF_INITECC, &nand->NFCONF);
+ writel(readl(&nand->nfconf) | S3C2410_NFCONF_INITECC, &nand->nfconf);
}
static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
@@ -114,7 +114,7 @@ int board_nand_init(struct nand_chip *nand)
debugX(1, "board_nand_init()\n");
- writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
+ writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
/* initialize hardware */
twrph0 = 3;
@@ -125,10 +125,10 @@ int board_nand_init(struct nand_chip *nand)
cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
- writel(cfg, &nand_reg->NFCONF);
+ writel(cfg, &nand_reg->nfconf);
/* initialize nand_chip data structure */
- nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA;
+ nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->nfdata;
/* read_buf and write_buf are default */
/* read_byte and write_byte are default */
diff --git a/drivers/rtc/s3c24x0_rtc.c b/drivers/rtc/s3c24x0_rtc.c
index 04de5ca..b4c59cf 100644
--- a/drivers/rtc/s3c24x0_rtc.c
+++ b/drivers/rtc/s3c24x0_rtc.c
@@ -43,17 +43,17 @@ typedef enum {
} RTC_ACCESS;
-static inline void SetRTC_Access(RTC_ACCESS a)
+static inline void set_rtc_access(RTC_ACCESS a)
{
struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc();
switch (a) {
case RTC_ENABLE:
- writeb(readb(&rtc->RTCCON) | 0x01, &rtc->RTCCON);
+ writeb(readb(&rtc->rtccon) | 0x01, &rtc->rtccon);
break;
case RTC_DISABLE:
- writeb(readb(&rtc->RTCCON) & ~0x01, &rtc->RTCCON);
+ writeb(readb(&rtc->rtccon) & ~0x01, &rtc->rtccon);
break;
}
}
@@ -67,30 +67,30 @@ int rtc_get(struct rtc_time *tmp)
uchar a_sec, a_min, a_hour, a_date, a_mon, a_year, a_armed;
/* enable access to RTC registers */
- SetRTC_Access(RTC_ENABLE);
+ set_rtc_access(RTC_ENABLE);
/* read RTC registers */
do {
- sec = readb(&rtc->BCDSEC);
- min = readb(&rtc->BCDMIN);
- hour = readb(&rtc->BCDHOUR);
- mday = readb(&rtc->BCDDATE);
- wday = readb(&rtc->BCDDAY);
- mon = readb(&rtc->BCDMON);
- year = readb(&rtc->BCDYEAR);
- } while (sec != readb(&rtc->BCDSEC));
+ sec = readb(&rtc->bcdsec);
+ min = readb(&rtc->bcdmin);
+ hour = readb(&rtc->bcdhour);
+ mday = readb(&rtc->bcddate);
+ wday = readb(&rtc->bcdday);
+ mon = readb(&rtc->bcdmon);
+ year = readb(&rtc->bcdyear);
+ } while (sec != readb(&rtc->bcdsec));
/* read ALARM registers */
- a_sec = readb(&rtc->ALMSEC);
- a_min = readb(&rtc->ALMMIN);
- a_hour = readb(&rtc->ALMHOUR);
- a_date = readb(&rtc->ALMDATE);
- a_mon = readb(&rtc->ALMMON);
- a_year = readb(&rtc->ALMYEAR);
- a_armed = readb(&rtc->RTCALM);
+ a_sec = readb(&rtc->almsec);
+ a_min = readb(&rtc->almmin);
+ a_hour = readb(&rtc->almhour);
+ a_date = readb(&rtc->almdate);
+ a_mon = readb(&rtc->almmon);
+ a_year = readb(&rtc->almyear);
+ a_armed = readb(&rtc->rtcalm);
/* disable access to RTC registers */
- SetRTC_Access(RTC_DISABLE);
+ set_rtc_access(RTC_DISABLE);
#ifdef RTC_DEBUG
printf("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
@@ -142,19 +142,19 @@ int rtc_set(struct rtc_time *tmp)
sec = bin2bcd(tmp->tm_sec);
/* enable access to RTC registers */
- SetRTC_Access(RTC_ENABLE);
+ set_rtc_access(RTC_ENABLE);
/* write RTC registers */
- writeb(sec, &rtc->BCDSEC);
- writeb(min, &rtc->BCDMIN);
- writeb(hour, &rtc->BCDHOUR);
- writeb(mday, &rtc->BCDDATE);
- writeb(wday, &rtc->BCDDAY);
- writeb(mon, &rtc->BCDMON);
- writeb(year, &rtc->BCDYEAR);
+ writeb(sec, &rtc->bcdsec);
+ writeb(min, &rtc->bcdmin);
+ writeb(hour, &rtc->bcdhour);
+ writeb(mday, &rtc->bcddate);
+ writeb(wday, &rtc->bcdday);
+ writeb(mon, &rtc->bcdmon);
+ writeb(year, &rtc->bcdyear);
/* disable access to RTC registers */
- SetRTC_Access(RTC_DISABLE);
+ set_rtc_access(RTC_DISABLE);
return 0;
}
@@ -163,8 +163,8 @@ void rtc_reset(void)
{
struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc();
- writeb((readb(&rtc->RTCCON) & ~0x06) | 0x08, &rtc->RTCCON);
- writeb(readb(&rtc->RTCCON) & ~(0x08 | 0x01), &rtc->RTCCON);
+ writeb((readb(&rtc->rtccon) & ~0x06) | 0x08, &rtc->rtccon);
+ writeb(readb(&rtc->rtccon) & ~(0x08 | 0x01), &rtc->rtccon);
}
#endif
diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c
index 5dd4dd8..a613229 100644
--- a/drivers/serial/serial_s3c24x0.c
+++ b/drivers/serial/serial_s3c24x0.c
@@ -100,7 +100,7 @@ void _serial_setbrg(const int dev_index)
/* value is calculated so : (int)(PCLK/16./baudrate) -1 */
reg = get_PCLK() / (16 * gd->baudrate) - 1;
- writel(reg, &uart->UBRDIV);
+ writel(reg, &uart->ubrdiv);
for (i = 0; i < 100; i++)
/* Delay */ ;
}
@@ -130,26 +130,26 @@ static int serial_init_dev(const int dev_index)
#endif
/* FIFO enable, Tx/Rx FIFO clear */
- writel(0x07, &uart->UFCON);
- writel(0x0, &uart->UMCON);
+ writel(0x07, &uart->ufcon);
+ writel(0x0, &uart->umcon);
/* Normal,No parity,1 stop,8 bit */
- writel(0x3, &uart->ULCON);
+ writel(0x3, &uart->ulcon);
/*
* tx=level,rx=edge,disable timeout int.,enable rx error int.,
* normal,interrupt or polling
*/
- writel(0x245, &uart->UCON);
+ writel(0x245, &uart->ucon);
#ifdef CONFIG_HWFLOW
- writel(0x1, &uart->UMCON); /* RTS up */
+ writel(0x1, &uart->umcon); /* RTS up */
#endif
/* FIXME: This is sooooooooooooooooooo ugly */
#if defined(CONFIG_ARCH_GTA02_v1) || defined(CONFIG_ARCH_GTA02_v2)
/* we need auto hw flow control on the gsm and gps port */
if (dev_index == 0 || dev_index == 1)
- writel(0x10, &uart->UMCON);
+ writel(0x10, &uart->umcon);
#endif
_serial_setbrg(dev_index);
@@ -175,10 +175,10 @@ int _serial_getc(const int dev_index)
{
struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
- while (!(readl(&uart->UTRSTAT) & 0x1))
+ while (!(readl(&uart->utrstat) & 0x1))
/* wait for character to arrive */ ;
- return readb(&uart->URXH) & 0xff;
+ return readb(&uart->urxh) & 0xff;
}
#if defined(CONFIG_SERIAL_MULTI)
@@ -236,15 +236,15 @@ void _serial_putc(const char c, const int dev_index)
return;
#endif
- while (!(readl(&uart->UTRSTAT) & 0x2))
+ while (!(readl(&uart->utrstat) & 0x2))
/* wait for room in the tx FIFO */ ;
#ifdef CONFIG_HWFLOW
- while (hwflow && !(readl(&uart->UMSTAT) & 0x1))
+ while (hwflow && !(readl(&uart->umstat) & 0x1))
/* Wait for CTS up */ ;
#endif
- writeb(c, &uart->UTXH);
+ writeb(c, &uart->utxh);
/* If \n, also do \r */
if (c == '\n')
@@ -271,7 +271,7 @@ int _serial_tstc(const int dev_index)
{
struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
- return readl(&uart->UTRSTAT) & 0x1;
+ return readl(&uart->utrstat) & 0x1;
}
#if defined(CONFIG_SERIAL_MULTI)
diff --git a/include/asm-arm/arch-s3c24x0/s3c24x0.h
b/include/asm-arm/arch-s3c24x0/s3c24x0.h
index 15f53dd..db29bfd 100644
--- a/include/asm-arm/arch-s3c24x0/s3c24x0.h
+++ b/include/asm-arm/arch-s3c24x0/s3c24x0.h
@@ -33,73 +33,73 @@
/* Memory controller (see manual chapter 5) */
struct s3c24x0_memctl {
- u32 BWSCON;
- u32 BANKCON[8];
- u32 REFRESH;
- u32 BANKSIZE;
- u32 MRSRB6;
- u32 MRSRB7;
+ u32 bwscon;
+ u32 bankcon[8];
+ u32 refresh;
+ u32 banksize;
+ u32 mrsrb6;
+ u32 mrsrb7;
};
/* USB HOST (see manual chapter 12) */
struct s3c24x0_usb_host {
- u32 HcRevision;
- u32 HcControl;
- u32 HcCommonStatus;
- u32 HcInterruptStatus;
- u32 HcInterruptEnable;
- u32 HcInterruptDisable;
- u32 HcHCCA;
- u32 HcPeriodCuttendED;
- u32 HcControlHeadED;
- u32 HcControlCurrentED;
- u32 HcBulkHeadED;
- u32 HcBuldCurrentED;
- u32 HcDoneHead;
- u32 HcRmInterval;
- u32 HcFmRemaining;
- u32 HcFmNumber;
- u32 HcPeriodicStart;
- u32 HcLSThreshold;
- u32 HcRhDescriptorA;
- u32 HcRhDescriptorB;
- u32 HcRhStatus;
- u32 HcRhPortStatus1;
- u32 HcRhPortStatus2;
+ u32 hc_revision;
+ u32 hc_control;
+ u32 hc_common_status;
+ u32 hc_interrupt_status;
+ u32 hc_interrupt_enable;
+ u32 hc_interrupt_disable;
+ u32 hc_hcca;
+ u32 hc_period_cuttend_ed;
+ u32 hc_control_head_ed;
+ u32 hc_control_current_ed;
+ u32 hc_bulk_head_ed;
+ u32 hc_buld_current_ed;
+ u32 hc_done_head;
+ u32 hc_rm_interval;
+ u32 hc_fm_remaining;
+ u32 hc_fm_number;
+ u32 hc_periodic_start;
+ u32 hc_ls_threshold;
+ u32 hc_rh_descriptor_a;
+ u32 hc_rh_descriptor_b;
+ u32 hc_rh_status;
+ u32 hc_rh_port_status1;
+ u32 hc_rh_port_status2;
};
/* INTERRUPT (see manual chapter 14) */
struct s3c24x0_interrupt {
- u32 SRCPND;
- u32 INTMOD;
- u32 INTMSK;
- u32 PRIORITY;
- u32 INTPND;
- u32 INTOFFSET;
+ u32 srcpnd;
+ u32 intmod;
+ u32 intmsk;
+ u32 priority;
+ u32 intpnd;
+ u32 intoffset;
#ifdef CONFIG_S3C2410
- u32 SUBSRCPND;
- u32 INTSUBMSK;
+ u32 subsrcpnd;
+ u32 intsubmsk;
#endif
};
/* DMAS (see manual chapter 8) */
struct s3c24x0_dma {
- u32 DISRC;
+ u32 disrc;
#ifdef CONFIG_S3C2410
- u32 DISRCC;
+ u32 disrcc;
#endif
- u32 DIDST;
+ u32 didst;
#ifdef CONFIG_S3C2410
- u32 DIDSTC;
+ u32 didstc;
#endif
- u32 DCON;
- u32 DSTAT;
- u32 DCSRC;
- u32 DCDST;
- u32 DMASKTRIG;
+ u32 dcon;
+ u32 dstat;
+ u32 dcsrc;
+ u32 dcdst;
+ u32 dmasktrig;
#ifdef CONFIG_S3C2400
u32 res[1];
#endif
@@ -116,90 +116,90 @@ struct s3c24x0_dmas {
/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
/* (see S3C2410 manual chapter 7) */
struct s3c24x0_clock_power {
- u32 LOCKTIME;
- u32 MPLLCON;
- u32 UPLLCON;
- u32 CLKCON;
- u32 CLKSLOW;
- u32 CLKDIVN;
+ u32 locktime;
+ u32 mpllcon;
+ u32 upllcon;
+ u32 clkcon;
+ u32 clkslow;
+ u32 clkdivn;
};
/* LCD CONTROLLER (see manual chapter 15) */
struct s3c24x0_lcd {
- u32 LCDCON1;
- u32 LCDCON2;
- u32 LCDCON3;
- u32 LCDCON4;
- u32 LCDCON5;
- u32 LCDSADDR1;
- u32 LCDSADDR2;
- u32 LCDSADDR3;
- u32 REDLUT;
- u32 GREENLUT;
- u32 BLUELUT;
+ u32 lcdcon1;
+ u32 lcdcon2;
+ u32 lcdcon3;
+ u32 lcdcon4;
+ u32 lcdcon5;
+ u32 lcdsaddr1;
+ u32 lcdsaddr2;
+ u32 lcdsaddr3;
+ u32 redlut;
+ u32 greenlut;
+ u32 bluelut;
u32 res[8];
- u32 DITHMODE;
- u32 TPAL;
+ u32 dithmode;
+ u32 tpal;
#ifdef CONFIG_S3C2410
- u32 LCDINTPND;
- u32 LCDSRCPND;
- u32 LCDINTMSK;
- u32 LPCSEL;
+ u32 lcdintpnd;
+ u32 lcdsrcpnd;
+ u32 lcdintmsk;
+ u32 lpcsel;
#endif
};
/* NAND FLASH (see S3C2410 manual chapter 6) */
struct s3c2410_nand {
- u32 NFCONF;
- u32 NFCMD;
- u32 NFADDR;
- u32 NFDATA;
- u32 NFSTAT;
- u32 NFECC;
+ u32 nfconf;
+ u32 nfcmd;
+ u32 nfaddr;
+ u32 nfdata;
+ u32 nfstat;
+ u32 nfecc;
};
/* UART (see manual chapter 11) */
struct s3c24x0_uart {
- u32 ULCON;
- u32 UCON;
- u32 UFCON;
- u32 UMCON;
- u32 UTRSTAT;
- u32 UERSTAT;
- u32 UFSTAT;
- u32 UMSTAT;
+ u32 ulcon;
+ u32 ucon;
+ u32 ufcon;
+ u32 umcon;
+ u32 utrstat;
+ u32 uerstat;
+ u32 ufstat;
+ u32 umstat;
#ifdef __BIG_ENDIAN
u8 res1[3];
- u8 UTXH;
+ u8 utxh;
u8 res2[3];
- u8 URXH;
+ u8 urxh;
#else /* Little Endian */
- u8 UTXH;
+ u8 utxh;
u8 res1[3];
- u8 URXH;
+ u8 urxh;
u8 res2[3];
#endif
- u32 UBRDIV;
+ u32 ubrdiv;
};
/* PWM TIMER (see manual chapter 10) */
struct s3c24x0_timer {
- u32 TCNTB;
- u32 TCMPB;
- u32 TCNTO;
+ u32 tcntb;
+ u32 tcmpb;
+ u32 tcnto;
};
struct s3c24x0_timers {
- u32 TCFG0;
- u32 TCFG1;
- u32 TCON;
+ u32 tcfg0;
+ u32 tcfg1;
+ u32 tcon;
struct s3c24x0_timer ch[4];
- u32 TCNTB4;
- u32 TCNTO4;
+ u32 tcntb4;
+ u32 tcnto4;
};
@@ -207,9 +207,9 @@ struct s3c24x0_timers {
struct s3c24x0_usb_dev_fifos {
#ifdef __BIG_ENDIAN
u8 res[3];
- u8 EP_FIFO_REG;
+ u8 ep_fifo_reg;
#else /* little endian */
- u8 EP_FIFO_REG;
+ u8 ep_fifo_reg;
u8 res[3];
#endif
};
@@ -217,29 +217,29 @@ struct s3c24x0_usb_dev_fifos {
struct s3c24x0_usb_dev_dmas {
#ifdef __BIG_ENDIAN
u8 res1[3];
- u8 EP_DMA_CON;
+ u8 ep_dma_con;
u8 res2[3];
- u8 EP_DMA_UNIT;
+ u8 ep_dma_unit;
u8 res3[3];
- u8 EP_DMA_FIFO;
+ u8 ep_dma_fifo;
u8 res4[3];
- u8 EP_DMA_TTC_L;
+ u8 ep_dma_ttc_l;
u8 res5[3];
- u8 EP_DMA_TTC_M;
+ u8 ep_dma_ttc_m;
u8 res6[3];
- u8 EP_DMA_TTC_H;
+ u8 ep_dma_ttc_h;
#else /* little endian */
- u8 EP_DMA_CON;
+ u8 ep_dma_con;
u8 res1[3];
- u8 EP_DMA_UNIT;
+ u8 ep_dma_unit;
u8 res2[3];
- u8 EP_DMA_FIFO;
+ u8 ep_dma_fifo;
u8 res3[3];
- u8 EP_DMA_TTC_L;
+ u8 ep_dma_ttc_l;
u8 res4[3];
- u8 EP_DMA_TTC_M;
+ u8 ep_dma_ttc_m;
u8 res5[3];
- u8 EP_DMA_TTC_H;
+ u8 ep_dma_ttc_h;
u8 res6[3];
#endif
};
@@ -247,69 +247,69 @@ struct s3c24x0_usb_dev_dmas {
struct s3c24x0_usb_device {
#ifdef __BIG_ENDIAN
u8 res1[3];
- u8 FUNC_ADDR_REG;
+ u8 func_addr_reg;
u8 res2[3];
- u8 PWR_REG;
+ u8 pwr_reg;
u8 res3[3];
- u8 EP_INT_REG;
+ u8 ep_int_reg;
u8 res4[15];
- u8 USB_INT_REG;
+ u8 usb_int_reg;
u8 res5[3];
- u8 EP_INT_EN_REG;
+ u8 ep_int_en_reg;
u8 res6[15];
- u8 USB_INT_EN_REG;
+ u8 usb_int_en_reg;
u8 res7[3];
- u8 FRAME_NUM1_REG;
+ u8 frame_num1_reg;
u8 res8[3];
- u8 FRAME_NUM2_REG;
+ u8 frame_num2_reg;
u8 res9[3];
- u8 INDEX_REG;
+ u8 index_reg;
u8 res10[7];
- u8 MAXP_REG;
+ u8 maxp_reg;
u8 res11[3];
- u8 EP0_CSR_IN_CSR1_REG;
+ u8 ep0_csr_in_csr1_reg;
u8 res12[3];
- u8 IN_CSR2_REG;
+ u8 in_csr2_reg;
u8 res13[7];
- u8 OUT_CSR1_REG;
+ u8 out_csr1_reg;
u8 res14[3];
- u8 OUT_CSR2_REG;
+ u8 out_csr2_reg;
u8 res15[3];
- u8 OUT_FIFO_CNT1_REG;
+ u8 out_fifo_cnt1_reg;
u8 res16[3];
- u8 OUT_FIFO_CNT2_REG;
+ u8 out_fifo_cnt2_reg;
#else /* little endian */
- u8 FUNC_ADDR_REG;
+ u8 func_addr_reg;
u8 res1[3];
- u8 PWR_REG;
+ u8 pwr_reg;
u8 res2[3];
- u8 EP_INT_REG;
+ u8 ep_int_reg;
u8 res3[15];
- u8 USB_INT_REG;
+ u8 usb_int_reg;
u8 res4[3];
- u8 EP_INT_EN_REG;
+ u8 ep_int_en_reg;
u8 res5[15];
- u8 USB_INT_EN_REG;
+ u8 usb_int_en_reg;
u8 res6[3];
- u8 FRAME_NUM1_REG;
+ u8 frame_num1_reg;
u8 res7[3];
- u8 FRAME_NUM2_REG;
+ u8 frame_num2_reg;
u8 res8[3];
- u8 INDEX_REG;
+ u8 index_reg;
u8 res9[7];
- u8 MAXP_REG;
+ u8 maxp_reg;
u8 res10[7];
- u8 EP0_CSR_IN_CSR1_REG;
+ u8 ep0_csr_in_csr1_reg;
u8 res11[3];
- u8 IN_CSR2_REG;
+ u8 in_csr2_reg;
u8 res12[3];
- u8 OUT_CSR1_REG;
+ u8 out_csr1_reg;
u8 res13[7];
- u8 OUT_CSR2_REG;
+ u8 out_csr2_reg;
u8 res14[3];
- u8 OUT_FIFO_CNT1_REG;
+ u8 out_fifo_cnt1_reg;
u8 res15[3];
- u8 OUT_FIFO_CNT2_REG;
+ u8 out_fifo_cnt2_reg;
u8 res16[3];
#endif /* __BIG_ENDIAN */
struct s3c24x0_usb_dev_fifos fifo[5];
@@ -319,18 +319,18 @@ struct s3c24x0_usb_device {
/* WATCH DOG TIMER (see manual chapter 18) */
struct s3c24x0_watchdog {
- u32 WTCON;
- u32 WTDAT;
- u32 WTCNT;
+ u32 wtcon;
+ u32 wtdat;
+ u32 wtcnt;
};
/* IIC (see manual chapter 20) */
struct s3c24x0_i2c {
- u32 IICCON;
- u32 IICSTAT;
- u32 IICADD;
- u32 IICDS;
+ u32 iiccon;
+ u32 iicstat;
+ u32 iicadd;
+ u32 iicds;
};
@@ -338,25 +338,25 @@ struct s3c24x0_i2c {
struct s3c24x0_i2s {
#ifdef __BIG_ENDIAN
u16 res1;
- u16 IISCON;
+ u16 iiscon;
u16 res2;
- u16 IISMOD;
+ u16 iismod;
u16 res3;
- u16 IISPSR;
+ u16 iispsr;
u16 res4;
- u16 IISFCON;
+ u16 iisfcon;
u16 res5;
- u16 IISFIFO;
+ u16 iisfifo;
#else /* little endian */
- u16 IISCON;
+ u16 iiscon;
u16 res1;
- u16 IISMOD;
+ u16 iismod;
u16 res2;
- u16 IISPSR;
+ u16 iispsr;
u16 res3;
- u16 IISFCON;
+ u16 iisfcon;
u16 res4;
- u16 IISFIFO;
+ u16 iisfifo;
u16 res5;
#endif
};
@@ -365,87 +365,87 @@ struct s3c24x0_i2s {
/* I/O PORT (see manual chapter 9) */
struct s3c24x0_gpio {
#ifdef CONFIG_S3C2400
- u32 PACON;
- u32 PADAT;
+ u32 pacon;
+ u32 padat;
- u32 PBCON;
- u32 PBDAT;
- u32 PBUP;
+ u32 pbcon;
+ u32 pbdat;
+ u32 pbup;
- u32 PCCON;
- u32 PCDAT;
- u32 PCUP;
+ u32 pccon;
+ u32 pcdat;
+ u32 pcup;
- u32 PDCON;
- u32 PDDAT;
- u32 PDUP;
+ u32 pdcon;
+ u32 pddat;
+ u32 pdup;
- u32 PECON;
- u32 PEDAT;
- u32 PEUP;
+ u32 pecon;
+ u32 pedat;
+ u32 peup;
- u32 PFCON;
- u32 PFDAT;
- u32 PFUP;
+ u32 pfcon;
+ u32 pfdat;
+ u32 pfup;
- u32 PGCON;
- u32 PGDAT;
- u32 PGUP;
+ u32 pgcon;
+ u32 pgdat;
+ u32 pgup;
- u32 OPENCR;
+ u32 opencr;
- u32 MISCCR;
- u32 EXTINT;
+ u32 misccr;
+ u32 extint;
#endif
#ifdef CONFIG_S3C2410
- u32 GPACON;
- u32 GPADAT;
+ u32 gpacon;
+ u32 gpadat;
u32 res1[2];
- u32 GPBCON;
- u32 GPBDAT;
- u32 GPBUP;
+ u32 gpbcon;
+ u32 gpbdat;
+ u32 gpbup;
u32 res2;
- u32 GPCCON;
- u32 GPCDAT;
- u32 GPCUP;
+ u32 gpccon;
+ u32 gpcdat;
+ u32 gpcup;
u32 res3;
- u32 GPDCON;
- u32 GPDDAT;
- u32 GPDUP;
+ u32 gpdcon;
+ u32 gpddat;
+ u32 gpdup;
u32 res4;
- u32 GPECON;
- u32 GPEDAT;
- u32 GPEUP;
+ u32 gpecon;
+ u32 gpedat;
+ u32 gpeup;
u32 res5;
- u32 GPFCON;
- u32 GPFDAT;
- u32 GPFUP;
+ u32 gpfcon;
+ u32 gpfdat;
+ u32 gpfup;
u32 res6;
- u32 GPGCON;
- u32 GPGDAT;
- u32 GPGUP;
+ u32 gpgcon;
+ u32 gpgdat;
+ u32 gpgup;
u32 res7;
- u32 GPHCON;
- u32 GPHDAT;
- u32 GPHUP;
+ u32 gphcon;
+ u32 gphdat;
+ u32 gphup;
u32 res8;
- u32 MISCCR;
- u32 DCLKCON;
- u32 EXTINT0;
- u32 EXTINT1;
- u32 EXTINT2;
- u32 EINTFLT0;
- u32 EINTFLT1;
- u32 EINTFLT2;
- u32 EINTFLT3;
- u32 EINTMASK;
- u32 EINTPEND;
- u32 GSTATUS0;
- u32 GSTATUS1;
- u32 GSTATUS2;
- u32 GSTATUS3;
- u32 GSTATUS4;
+ u32 misccr;
+ u32 dclkcon;
+ u32 extint0;
+ u32 extint1;
+ u32 extint2;
+ u32 eintflt0;
+ u32 eintflt1;
+ u32 eintflt2;
+ u32 eintflt3;
+ u32 eintmask;
+ u32 eintpend;
+ u32 gstatus0;
+ u32 gstatus1;
+ u32 gstatus2;
+ u32 gstatus3;
+ u32 gstatus4;
#endif
};
@@ -454,74 +454,74 @@ struct s3c24x0_gpio {
struct s3c24x0_rtc {
#ifdef __BIG_ENDIAN
u8 res1[67];
- u8 RTCCON;
+ u8 rtccon;
u8 res2[3];
- u8 TICNT;
+ u8 ticnt;
u8 res3[11];
- u8 RTCALM;
+ u8 rtcalm;
u8 res4[3];
- u8 ALMSEC;
+ u8 almsec;
u8 res5[3];
- u8 ALMMIN;
+ u8 almmin;
u8 res6[3];
- u8 ALMHOUR;
+ u8 almhour;
u8 res7[3];
- u8 ALMDATE;
+ u8 almdate;
u8 res8[3];
- u8 ALMMON;
+ u8 almmon;
u8 res9[3];
- u8 ALMYEAR;
+ u8 almyear;
u8 res10[3];
- u8 RTCRST;
+ u8 rtcrst;
u8 res11[3];
- u8 BCDSEC;
+ u8 bcdsec;
u8 res12[3];
- u8 BCDMIN;
+ u8 bcdmin;
u8 res13[3];
- u8 BCDHOUR;
+ u8 bcdhour;
u8 res14[3];
- u8 BCDDATE;
+ u8 bcddate;
u8 res15[3];
- u8 BCDDAY;
+ u8 bcdday;
u8 res16[3];
- u8 BCDMON;
+ u8 bcdmon;
u8 res17[3];
- u8 BCDYEAR;
+ u8 bcdyear;
#else /* little endian */
u8 res0[64];
- u8 RTCCON;
+ u8 rtccon;
u8 res1[3];
- u8 TICNT;
+ u8 ticnt;
u8 res2[11];
- u8 RTCALM;
+ u8 rtcalm;
u8 res3[3];
- u8 ALMSEC;
+ u8 almsec;
u8 res4[3];
- u8 ALMMIN;
+ u8 almmin;
u8 res5[3];
- u8 ALMHOUR;
+ u8 almhour;
u8 res6[3];
- u8 ALMDATE;
+ u8 almdate;
u8 res7[3];
- u8 ALMMON;
+ u8 almmon;
u8 res8[3];
- u8 ALMYEAR;
+ u8 almyear;
u8 res9[3];
- u8 RTCRST;
+ u8 rtcrst;
u8 res10[3];
- u8 BCDSEC;
+ u8 bcdsec;
u8 res11[3];
- u8 BCDMIN;
+ u8 bcdmin;
u8 res12[3];
- u8 BCDHOUR;
+ u8 bcdhour;
u8 res13[3];
- u8 BCDDATE;
+ u8 bcddate;
u8 res14[3];
- u8 BCDDAY;
+ u8 bcdday;
u8 res15[3];
- u8 BCDMON;
+ u8 bcdmon;
u8 res16[3];
- u8 BCDYEAR;
+ u8 bcdyear;
u8 res17[3];
#endif
};
@@ -529,34 +529,34 @@ struct s3c24x0_rtc {
/* ADC (see manual chapter 16) */
struct s3c2400_adc {
- u32 ADCCON;
- u32 ADCDAT;
+ u32 adccon;
+ u32 adcdat;
};
/* ADC (see manual chapter 16) */
struct s3c2410_adc {
- u32 ADCCON;
- u32 ADCTSC;
- u32 ADCDLY;
- u32 ADCDAT0;
- u32 ADCDAT1;
+ u32 adccon;
+ u32 adctsc;
+ u32 adcdly;
+ u32 adcdat0;
+ u32 adcdat1;
};
/* SPI (see manual chapter 22) */
struct s3c24x0_spi_channel {
- u8 SPCON;
+ u8 spcon;
u8 res1[3];
- u8 SPSTA;
+ u8 spsta;
u8 res2[3];
- u8 SPPIN;
+ u8 sppin;
u8 res3[3];
- u8 SPPRE;
+ u8 sppre;
u8 res4[3];
- u8 SPTDAT;
+ u8 sptdat;
u8 res5[3];
- u8 SPRDAT;
+ u8 sprdat;
u8 res6[3];
u8 res7[16];
};
@@ -570,53 +570,53 @@ struct s3c24x0_spi {
struct s3c2400_mmc {
#ifdef __BIG_ENDIAN
u8 res1[3];
- u8 MMCON;
+ u8 mmcon;
u8 res2[3];
- u8 MMCRR;
+ u8 mmcrr;
u8 res3[3];
- u8 MMFCON;
+ u8 mmfcon;
u8 res4[3];
- u8 MMSTA;
+ u8 mmsta;
u16 res5;
- u16 MMFSTA;
+ u16 mmfsta;
u8 res6[3];
- u8 MMPRE;
+ u8 mmpre;
u16 res7;
- u16 MMLEN;
+ u16 mmlen;
u8 res8[3];
- u8 MMCR7;
- u32 MMRSP[4];
+ u8 mmcr7;
+ u32 mmrsp[4];
u8 res9[3];
- u8 MMCMD0;
- u32 MMCMD1;
+ u8 mmcmd0;
+ u32 mmcmd1;
u16 res10;
- u16 MMCR16;
+ u16 mmcr16;
u8 res11[3];
- u8 MMDAT;
+ u8 mmdat;
#else
- u8 MMCON;
+ u8 mmcon;
u8 res1[3];
- u8 MMCRR;
+ u8 mmcrr;
u8 res2[3];
- u8 MMFCON;
+ u8 mmfcon;
u8 res3[3];
- u8 MMSTA;
+ u8 mmsta;
u8 res4[3];
- u16 MMFSTA;
+ u16 mmfsta;
u16 res5;
- u8 MMPRE;
+ u8 mmpre;
u8 res6[3];
- u16 MMLEN;
+ u16 mmlen;
u16 res7;
- u8 MMCR7;
+ u8 mmcr7;
u8 res8[3];
- u32 MMRSP[4];
- u8 MMCMD0;
+ u32 mmrsp[4];
+ u8 mmcmd0;
u8 res9[3];
- u32 MMCMD1;
- u16 MMCR16;
+ u32 mmcmd1;
+ u16 mmcr16;
u16 res10;
- u8 MMDAT;
+ u8 mmdat;
u8 res11[3];
#endif
};
@@ -624,29 +624,29 @@ struct s3c2400_mmc {
/* SD INTERFACE (see S3C2410 manual chapter 19) */
struct s3c2410_sdi {
- u32 SDICON;
- u32 SDIPRE;
- u32 SDICARG;
- u32 SDICCON;
- u32 SDICSTA;
- u32 SDIRSP0;
- u32 SDIRSP1;
- u32 SDIRSP2;
- u32 SDIRSP3;
- u32 SDIDTIMER;
- u32 SDIBSIZE;
- u32 SDIDCON;
- u32 SDIDCNT;
- u32 SDIDSTA;
- u32 SDIFSTA;
+ u32 sdicon;
+ u32 sdipre;
+ u32 sdicarg;
+ u32 sdiccon;
+ u32 sdicsta;
+ u32 sdirsp0;
+ u32 sdirsp1;
+ u32 sdirsp2;
+ u32 sdirsp3;
+ u32 sdidtimer;
+ u32 sdibsize;
+ u32 sdidcon;
+ u32 sdidcnt;
+ u32 sdidsta;
+ u32 sdifsta;
#ifdef __BIG_ENDIAN
u8 res[3];
- u8 SDIDAT;
+ u8 sdidat;
#else
- u8 SDIDAT;
+ u8 sdidat;
u8 res[3];
#endif
- u32 SDIIMSK;
+ u32 sdiimsk;
};
#endif /*__S3C24X0_H__*/
--
1.6.1.2
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