2017-08-19 0:02 GMT+02:00 Pau Pajuelo <ppaj...@gmail.com>:
> Tested-by: Pau Pajuelo <ppaj...@gmail.com>
>
> 2017-08-17 3:06 GMT+02:00 Ladislav Michl <la...@linux-mips.org>:
>> Avoid cluttering board file with CONFIG_SPL_BUILD ifdefs
>> by moving SPL related functions into separate file.
>>
>> Signed-off-by: Ladislav Michl <la...@linux-mips.org>
>> ---
>> board/isee/igep00x0/Makefile | 6 +-
>> board/isee/igep00x0/common.c | 80 ++++++++++++++++++++++++++
>> board/isee/igep00x0/igep00x0.c | 128
>> -----------------------------------------
>> board/isee/igep00x0/spl.c | 64 +++++++++++++++++++++
>> 4 files changed, 149 insertions(+), 129 deletions(-)
>>
>> diff --git a/board/isee/igep00x0/Makefile b/board/isee/igep00x0/Makefile
>> index 68b151c3c5..74594da771 100644
>> --- a/board/isee/igep00x0/Makefile
>> +++ b/board/isee/igep00x0/Makefile
>> @@ -5,4 +5,8 @@
>> # SPDX-License-Identifier: GPL-2.0+
>> #
>>
>> -obj-y := igep00x0.o
>> +ifdef CONFIG_SPL_BUILD
>> +obj-y := spl.o common.o
>> +else
>> +obj-y := igep00x0.o common.o
>> +endif
>> diff --git a/board/isee/igep00x0/common.c b/board/isee/igep00x0/common.c
>> new file mode 100644
>> index 0000000000..b8f1c14f6a
>> --- /dev/null
>> +++ b/board/isee/igep00x0/common.c
>> @@ -0,0 +1,80 @@
>> +/*
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +#include <common.h>
>> +#include <twl4030.h>
>> +#include <asm/io.h>
>> +#include <asm/omap_mmc.h>
>> +#include <asm/arch/mux.h>
>> +#include <asm/arch/sys_proto.h>
>> +#include <jffs2/load_kernel.h>
>> +#include <linux/mtd/nand.h>
>> +#include "igep00x0.h"
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +/*
>> + * Routine: set_muxconf_regs
>> + * Description: Setting up the configuration Mux registers specific to the
>> + * hardware. Many pins need to be moved from protect to primary
>> + * mode.
>> + */
>> +void set_muxconf_regs(void)
>> +{
>> + MUX_DEFAULT();
>> +
>> +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
>> + MUX_IGEP0020();
>> +#endif
>> +
>> +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
>> + MUX_IGEP0030();
>> +#endif
>> +}
>> +
>> +/*
>> + * Routine: board_init
>> + * Description: Early hardware init.
>> + */
>> +int board_init(void)
>> +{
>> + int loops = 100;
>> +
>> + /* find out flash memory type, assume NAND first */
>> + gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
>> + gpmc_init();
>> +
>> + /* Issue a RESET and then READID */
>> + writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
>> + writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
>> + while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
>> + != NAND_STATUS_READY) {
>> + udelay(1);
>> + if (--loops == 0) {
>> + gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
>> + gpmc_init(); /* reinitialize for OneNAND */
>> + break;
>> + }
>> + }
>> +
>> + /* boot param addr */
>> + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
>> +
>> +#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
>> + status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
>> +#endif
>> +
>> + return 0;
>> +}
>> +
>> +#if defined(CONFIG_MMC)
>> +int board_mmc_init(bd_t *bis)
>> +{
>> + return omap_mmc_init(0, 0, 0, -1, -1);
>> +}
>> +
>> +void board_mmc_power_init(void)
>> +{
>> + twl4030_power_mmc_init(0);
>> +}
>> +#endif
>> diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
>> index a7a75601dd..74f9bab093 100644
>> --- a/board/isee/igep00x0/igep00x0.c
>> +++ b/board/isee/igep00x0/igep00x0.c
>> @@ -20,15 +20,12 @@
>> #include <asm/mach-types.h>
>> #include <linux/mtd/mtd.h>
>> #include <linux/mtd/nand.h>
>> -#include <linux/mtd/nand.h>
>> #include <linux/mtd/onenand.h>
>> #include <jffs2/load_kernel.h>
>> #include <mtd_node.h>
>> #include <fdt_support.h>
>> #include "igep00x0.h"
>>
>> -DECLARE_GLOBAL_DATA_PTR;
>> -
>> static const struct ns16550_platdata igep_serial = {
>> .base = OMAP34XX_UART3,
>> .reg_shift = 2,
>> @@ -41,98 +38,6 @@ U_BOOT_DEVICE(igep_uart) = {
>> &igep_serial
>> };
>>
>> -/*
>> - * Routine: board_init
>> - * Description: Early hardware init.
>> - */
>> -int board_init(void)
>> -{
>> - int loops = 100;
>> -
>> - /* find out flash memory type, assume NAND first */
>> - gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
>> - gpmc_init();
>> -
>> - /* Issue a RESET and then READID */
>> - writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
>> - writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
>> - while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
>> - != NAND_STATUS_READY) {
>> - udelay(1);
>> - if (--loops == 0) {
>> - gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
>> - gpmc_init(); /* reinitialize for OneNAND */
>> - break;
>> - }
>> - }
>> -
>> - /* boot param addr */
>> - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
>> -
>> -#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
>> - status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
>> -#endif
>> -
>> - return 0;
>> -}
>> -
>> -#ifdef CONFIG_SPL_BUILD
>> -/*
>> - * Routine: get_board_mem_timings
>> - * Description: If we use SPL then there is no x-loader nor config header
>> - * so we have to setup the DDR timings ourself on both banks.
>> - */
>> -void get_board_mem_timings(struct board_sdrc_timings *timings)
>> -{
>> - int mfr, id, err = identify_nand_chip(&mfr, &id);
>> -
>> - timings->mr = MICRON_V_MR_165;
>> - if (!err) {
>> - switch (mfr) {
>> - case NAND_MFR_HYNIX:
>> - timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
>> - timings->ctrla = HYNIX_V_ACTIMA_200;
>> - timings->ctrlb = HYNIX_V_ACTIMB_200;
>> - break;
>> - case NAND_MFR_MICRON:
>> - timings->mcfg = MICRON_V_MCFG_200(256 << 20);
>> - timings->ctrla = MICRON_V_ACTIMA_200;
>> - timings->ctrlb = MICRON_V_ACTIMB_200;
>> - break;
>> - default:
>> - /* Should not happen... */
>> - break;
>> - }
>> - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
>> - gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
>> - } else {
>> - if (get_cpu_family() == CPU_OMAP34XX) {
>> - timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
>> - timings->ctrla = NUMONYX_V_ACTIMA_165;
>> - timings->ctrlb = NUMONYX_V_ACTIMB_165;
>> - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
>> - } else {
>> - timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
>> - timings->ctrla = NUMONYX_V_ACTIMA_200;
>> - timings->ctrlb = NUMONYX_V_ACTIMB_200;
>> - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
>> - }
>> - gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
>> - }
>> -}
>> -
>> -#ifdef CONFIG_SPL_OS_BOOT
>> -int spl_start_uboot(void)
>> -{
>> - /* break into full u-boot on 'c' */
>> - if (serial_tstc() && serial_getc() == 'c')
>> - return 1;
>> -
>> - return 0;
>> -}
>> -#endif
>> -#endif
>> -
>> int onenand_board_init(struct mtd_info *mtd)
>> {
>> if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
>> @@ -199,20 +104,6 @@ int board_eth_init(bd_t *bis)
>> static inline void setup_net_chip(void) {}
>> #endif
>>
>> -#if defined(CONFIG_MMC)
>> -int board_mmc_init(bd_t *bis)
>> -{
>> - return omap_mmc_init(0, 0, 0, -1, -1);
>> -}
>> -#endif
>> -
>> -#if defined(CONFIG_MMC)
>> -void board_mmc_power_init(void)
>> -{
>> - twl4030_power_mmc_init(0);
>> -}
>> -#endif
>> -
>> #ifdef CONFIG_OF_BOARD_SETUP
>> static int ft_enable_by_compatible(void *blob, char *compat, int enable)
>> {
>> @@ -292,22 +183,3 @@ void board_mtdparts_default(const char **mtdids, const
>> char **mtdparts)
>> *mtdparts = parts;
>> }
>> }
>> -
>> -/*
>> - * Routine: set_muxconf_regs
>> - * Description: Setting up the configuration Mux registers specific to the
>> - * hardware. Many pins need to be moved from protect to primary
>> - * mode.
>> - */
>> -void set_muxconf_regs(void)
>> -{
>> - MUX_DEFAULT();
>> -
>> -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
>> - MUX_IGEP0020();
>> -#endif
>> -
>> -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
>> - MUX_IGEP0030();
>> -#endif
>> -}
>> diff --git a/board/isee/igep00x0/spl.c b/board/isee/igep00x0/spl.c
>> new file mode 100644
>> index 0000000000..eb705cbe88
>> --- /dev/null
>> +++ b/board/isee/igep00x0/spl.c
>> @@ -0,0 +1,64 @@
>> +/*
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +#include <asm/io.h>
>> +#include <asm/arch/mem.h>
>> +#include <asm/arch/sys_proto.h>
>> +#include <jffs2/load_kernel.h>
>> +#include <linux/mtd/nand.h>
>> +#include "igep00x0.h"
>> +
>> +/*
>> + * Routine: get_board_mem_timings
>> + * Description: If we use SPL then there is no x-loader nor config header
>> + * so we have to setup the DDR timings ourself on both banks.
>> + */
>> +void get_board_mem_timings(struct board_sdrc_timings *timings)
>> +{
>> + int mfr, id, err = identify_nand_chip(&mfr, &id);
>> +
>> + timings->mr = MICRON_V_MR_165;
>> + if (!err) {
>> + switch (mfr) {
>> + case NAND_MFR_HYNIX:
>> + timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
>> + timings->ctrla = HYNIX_V_ACTIMA_200;
>> + timings->ctrlb = HYNIX_V_ACTIMB_200;
>> + break;
>> + case NAND_MFR_MICRON:
>> + timings->mcfg = MICRON_V_MCFG_200(256 << 20);
>> + timings->ctrla = MICRON_V_ACTIMA_200;
>> + timings->ctrlb = MICRON_V_ACTIMB_200;
>> + break;
>> + default:
>> + /* Should not happen... */
>> + break;
>> + }
>> + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
>> + gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
>> + } else {
>> + if (get_cpu_family() == CPU_OMAP34XX) {
>> + timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
>> + timings->ctrla = NUMONYX_V_ACTIMA_165;
>> + timings->ctrlb = NUMONYX_V_ACTIMB_165;
>> + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
>> + } else {
>> + timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
>> + timings->ctrla = NUMONYX_V_ACTIMA_200;
>> + timings->ctrlb = NUMONYX_V_ACTIMB_200;
>> + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
>> + }
>> + gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
>> + }
>> +}
>> +
>> +#ifdef CONFIG_SPL_OS_BOOT
>> +int spl_start_uboot(void)
>> +{
>> + /* break into full u-boot on 'c' */
>> + if (serial_tstc() && serial_getc() == 'c')
>> + return 1;
>> +
>> + return 0;
>> +}
>> +#endif
>> --
>> 2.11.0
>>
Ladis, thanks for this patch.
Acked-by: Enric Balletbo i Serra <enric.balle...@collabora.com>
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