From: Patrice Chotard <patrice.chot...@st.com>
Add FMC sdram node with associated new bindings value to managed
bank 1.
Signed-off-by: Patrice Chotard <patrice.chot...@st.com>
---
arch/arm/dts/stm32h743-pinctrl.dtsi | 69 ++++++++++++++++++++++++++++++++
arch/arm/dts/stm32h743.dtsi | 6 +++
arch/arm/dts/stm32h743i-disco.dts | 16 ++++++++
include/dt-bindings/memory/stm32-sdram.h | 7 ++++
4 files changed, 98 insertions(+)
diff --git a/arch/arm/dts/stm32h743-pinctrl.dtsi
b/arch/arm/dts/stm32h743-pinctrl.dtsi
index f32d086..d3e11d5 100644
--- a/arch/arm/dts/stm32h743-pinctrl.dtsi
+++ b/arch/arm/dts/stm32h743-pinctrl.dtsi
@@ -175,6 +175,75 @@
bias-disable;
};
};
+
+ fmc_pins: fmc@0 {
+ pins {
+ pinmux =
<STM32H7_PD0_FUNC_FMC_D2_FMC_DA2>,
+
<STM32H7_PD1_FUNC_FMC_D3_FMC_DA3>,
+
<STM32H7_PD8_FUNC_FMC_D13_FMC_DA13>,
+
<STM32H7_PD9_FUNC_FMC_D14_FMC_DA14>,
+
<STM32H7_PD10_FUNC_FMC_D15_FMC_DA15>,
+
<STM32H7_PD14_FUNC_FMC_D0_FMC_DA0>,
+
<STM32H7_PD15_FUNC_FMC_D1_FMC_DA1>,
+
+ <STM32H7_PE0_FUNC_FMC_NBL0>,
+ <STM32H7_PE1_FUNC_FMC_NBL1>,
+
<STM32H7_PE7_FUNC_FMC_D4_FMC_DA4>,
+
<STM32H7_PE8_FUNC_FMC_D5_FMC_DA5>,
+
<STM32H7_PE9_FUNC_FMC_D6_FMC_DA6>,
+
<STM32H7_PE10_FUNC_FMC_D7_FMC_DA7>,
+
<STM32H7_PE11_FUNC_FMC_D8_FMC_DA8>,
+
<STM32H7_PE12_FUNC_FMC_D9_FMC_DA9>,
+
<STM32H7_PE13_FUNC_FMC_D10_FMC_DA10>,
+
<STM32H7_PE14_FUNC_FMC_D11_FMC_DA11>,
+
<STM32H7_PE15_FUNC_FMC_D12_FMC_DA12>,
+
+ <STM32H7_PF0_FUNC_FMC_A0>,
+ <STM32H7_PF1_FUNC_FMC_A1>,
+ <STM32H7_PF2_FUNC_FMC_A2>,
+ <STM32H7_PF3_FUNC_FMC_A3>,
+ <STM32H7_PF4_FUNC_FMC_A4>,
+ <STM32H7_PF5_FUNC_FMC_A5>,
+
<STM32H7_PF11_FUNC_FMC_SDNRAS>,
+ <STM32H7_PF12_FUNC_FMC_A6>,
+ <STM32H7_PF13_FUNC_FMC_A7>,
+ <STM32H7_PF14_FUNC_FMC_A8>,
+ <STM32H7_PF15_FUNC_FMC_A9>,
+
+ <STM32H7_PG0_FUNC_FMC_A10>,
+ <STM32H7_PG1_FUNC_FMC_A11>,
+ <STM32H7_PG2_FUNC_FMC_A12>,
+
<STM32H7_PG4_FUNC_FMC_A14_FMC_BA0>,
+
<STM32H7_PG5_FUNC_FMC_A15_FMC_BA1>,
+ <STM32H7_PG8_FUNC_FMC_SDCLK>,
+
<STM32H7_PG15_FUNC_FMC_SDNCAS>,
+
+ <STM32H7_PH5_FUNC_FMC_SDNWE>,
+ <STM32H7_PH6_FUNC_FMC_SDNE1>,
+ <STM32H7_PH7_FUNC_FMC_SDCKE1>,
+ <STM32H7_PH8_FUNC_FMC_D16>,
+ <STM32H7_PH9_FUNC_FMC_D17>,
+ <STM32H7_PH10_FUNC_FMC_D18>,
+ <STM32H7_PH11_FUNC_FMC_D19>,
+ <STM32H7_PH12_FUNC_FMC_D20>,
+ <STM32H7_PH13_FUNC_FMC_D21>,
+ <STM32H7_PH14_FUNC_FMC_D22>,
+ <STM32H7_PH15_FUNC_FMC_D23>,
+
+ <STM32H7_PI0_FUNC_FMC_D24>,
+ <STM32H7_PI1_FUNC_FMC_D25>,
+ <STM32H7_PI2_FUNC_FMC_D26>,
+ <STM32H7_PI3_FUNC_FMC_D27>,
+ <STM32H7_PI4_FUNC_FMC_NBL2>,
+ <STM32H7_PI5_FUNC_FMC_NBL3>,
+ <STM32H7_PI6_FUNC_FMC_D28>,
+ <STM32H7_PI7_FUNC_FMC_D29>,
+ <STM32H7_PI9_FUNC_FMC_D30>,
+ <STM32H7_PI10_FUNC_FMC_D31>;
+
+ slew-rate = <3>;
+ };
+ };
};
};
};
diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi
index fd926a7..ca3faad 100644
--- a/arch/arm/dts/stm32h743.dtsi
+++ b/arch/arm/dts/stm32h743.dtsi
@@ -102,6 +102,12 @@
compatible = "syscon";
reg = <0x58024800 0x400>;
};
+
+ fmc: fmc@52004000 {
+ compatible = "st,stm32h7-fmc";
+ reg = <0x52004000 0x1000>;
+ clocks = <&rcc FMC_CK>;
+ };
};
};
diff --git a/arch/arm/dts/stm32h743i-disco.dts
b/arch/arm/dts/stm32h743i-disco.dts
index cc707d3..03af13d 100644
--- a/arch/arm/dts/stm32h743i-disco.dts
+++ b/arch/arm/dts/stm32h743i-disco.dts
@@ -43,6 +43,7 @@
/dts-v1/;
#include "stm32h743.dtsi"
#include "stm32h743-pinctrl.dtsi"
+#include <dt-bindings/memory/stm32-sdram.h>
/ {
model = "STMicroelectronics STM32H743i-Discovery board";
@@ -82,3 +83,18 @@
pinctrl-names = "default";
status = "okay";
};
+
+&fmc {
+ pinctrl-0 = <&fmc_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /* Memory configuration from sdram datasheet IS42S32800G-6BLI */
+ bank1: bank@1 {
+ st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32
BANKS_4
+ CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;
+ st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
+ TWR_1 TRCD_1>;
+ st,sdram-refcount = <1539>;
+ };
+};
diff --git a/include/dt-bindings/memory/stm32-sdram.h
b/include/dt-bindings/memory/stm32-sdram.h
index 89b719a..c2b911f 100644
--- a/include/dt-bindings/memory/stm32-sdram.h
+++ b/include/dt-bindings/memory/stm32-sdram.h
@@ -18,7 +18,9 @@
#define CAS_1 0x1
#define CAS_2 0x2
#define CAS_3 0x3
+#define SDCLK_DIS 0x0
#define SDCLK_2 0x2
+#define SDCLK_3 0x3
#define RD_BURST_EN 0x1
#define RD_BURST_DIS 0x0
#define RD_PIPE_DL_0 0x0
@@ -26,12 +28,17 @@
#define RD_PIPE_DL_2 0x2
/* Timing = value +1 cycles */
+#define TMRD_1 (1 - 1)
#define TMRD_2 (2 - 1)
+#define TXSR_1 (1 - 1)
#define TXSR_6 (6 - 1)
+#define TRAS_1 (1 - 1)
#define TRAS_4 (4 - 1)
#define TRC_6 (6 - 1)
+#define TWR_1 (1 - 1)
#define TWR_2 (2 - 1)
#define TRP_2 (2 - 1)
+#define TRCD_1 (1 - 1)
#define TRCD_2 (2 - 1)
#endif
--
1.9.1
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
