Update SVR as per the SOC document.
-LS2081A: 0x870919 -> 0x870918
-LS2041A: 0x870915 -> 0x870914
Signed-off-by: Santan Kumar <santan.ku...@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.j...@nxp.com>
Signed-off-by: Hou Zhiqiang <zhiqiang....@nxp.com>
---
arch/arm/include/asm/arch-fsl-layerscape/soc.h | 4 ++--
drivers/pci/pcie_layerscape.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index cc3b079..fae5730 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -55,8 +55,8 @@ struct cpu_type {
#define SVR_LS2084A 0x870910
#define SVR_LS2048A 0x870920
#define SVR_LS2044A 0x870930
-#define SVR_LS2081A 0x870919
-#define SVR_LS2041A 0x870915
+#define SVR_LS2081A 0x870918
+#define SVR_LS2041A 0x870914
#define SVR_DEV_LS2080A 0x8701
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 308b073..782e3ab 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -118,8 +118,8 @@
#define SVR_LS2084A 0x870910
#define SVR_LS2048A 0x870920
#define SVR_LS2044A 0x870930
-#define SVR_LS2081A 0x870919
-#define SVR_LS2041A 0x870915
+#define SVR_LS2081A 0x870918
+#define SVR_LS2041A 0x870914
/* LS1021a PCIE space */
#define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL
--
1.9.1
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