SDMMC-PWREN is a pin to control voltage for SDMMC IO, it may
be high active or low active, the dwmmc driver always assume
the sdmmc-pwren as high active.
Kernel treat this pin as fixed regulator instead of a pin from
controller, and then it can set in dts file upon board schematic,
that's a good solution, we can also do this in u-boot.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
drivers/pinctrl/rockchip/pinctrl_rk3328.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c
b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
index 716d02a..0995d9f 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
@@ -184,13 +184,11 @@ static void pinctrl_rk3328_sdmmc_config(struct
rk3328_grf_regs *grf,
if (com_iomux & IOMUX_SEL_SDMMC_MASK)
rk_clrsetreg(&grf->gpio0d_iomux,
GPIO0D6_SEL_MASK,
- GPIO0D6_SDMMC0_PWRENM1
- << GPIO0D6_SEL_SHIFT);
+ GPIO0D6_GPIO << GPIO0D6_SEL_SHIFT);
else
rk_clrsetreg(&grf->gpio2a_iomux,
GPIO2A7_SEL_MASK,
- GPIO2A7_SDMMC0_PWRENM0
- << GPIO2A7_SEL_SHIFT);
+ GPIO2A7_GPIO << GPIO2A7_SEL_SHIFT);
rk_clrsetreg(&grf->gpio1a_iomux,
GPIO1A0_SEL_MASK,
GPIO1A0_CARD_DATA_CLK_CMD_DETN
--
1.9.1
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