From: Jagan Teki <ja...@amarulasolutions.com>

- Give proper tab alignment for display_info_t structure
- Add tab spaces UART_PAD_CTRL and SPI_PAD_CTRL
- Give proper alignment of reg init values on setup_display
- Add space and newline on board_init_f

Cc: Stefano Babic <sba...@denx.de>
Cc: Fabio Estevam <fabio.este...@nxp.com>
Cc: Michael Trimarchi <mich...@amarulasolutions.com>
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
 board/freescale/imx6sabresd/imx6sabresd.c | 183 +++++++++++++++---------------
 1 file changed, 94 insertions(+), 89 deletions(-)

diff --git a/board/freescale/imx6sabresd/imx6sabresd.c 
b/board/freescale/imx6sabresd/imx6sabresd.c
index 64a44cb..7af18bc 100644
--- a/board/freescale/imx6sabresd/imx6sabresd.c
+++ b/board/freescale/imx6sabresd/imx6sabresd.c
@@ -27,12 +27,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
-       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
-       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
-                     PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
+                       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+                       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define SPI_PAD_CTRL   (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
 
 int dram_init(void)
 {
@@ -201,67 +200,72 @@ static void do_enable_hdmi(struct display_info_t const 
*dev)
        imx_enable_hdmi_phy();
 }
 
-struct display_info_t const displays[] = {{
-       .bus    = -1,
-       .addr   = 0,
-       .pixfmt = IPU_PIX_FMT_RGB666,
-       .detect = NULL,
-       .enable = enable_lvds,
-       .mode   = {
-               .name           = "Hannstar-XGA",
-               .refresh        = 60,
-               .xres           = 1024,
-               .yres           = 768,
-               .pixclock       = 15384,
-               .left_margin    = 160,
-               .right_margin   = 24,
-               .upper_margin   = 29,
-               .lower_margin   = 3,
-               .hsync_len      = 136,
-               .vsync_len      = 6,
-               .sync           = FB_SYNC_EXT,
-               .vmode          = FB_VMODE_NONINTERLACED
-} }, {
-       .bus    = -1,
-       .addr   = 0,
-       .pixfmt = IPU_PIX_FMT_RGB24,
-       .detect = detect_hdmi,
-       .enable = do_enable_hdmi,
-       .mode   = {
-               .name           = "HDMI",
-               .refresh        = 60,
-               .xres           = 1024,
-               .yres           = 768,
-               .pixclock       = 15384,
-               .left_margin    = 160,
-               .right_margin   = 24,
-               .upper_margin   = 29,
-               .lower_margin   = 3,
-               .hsync_len      = 136,
-               .vsync_len      = 6,
-               .sync           = FB_SYNC_EXT,
-               .vmode          = FB_VMODE_NONINTERLACED
-} }, {
-       .bus    = 0,
-       .addr   = 0,
-       .pixfmt = IPU_PIX_FMT_RGB24,
-       .detect = NULL,
-       .enable = enable_rgb,
-       .mode   = {
-               .name           = "SEIKO-WVGA",
-               .refresh        = 60,
-               .xres           = 800,
-               .yres           = 480,
-               .pixclock       = 29850,
-               .left_margin    = 89,
-               .right_margin   = 164,
-               .upper_margin   = 23,
-               .lower_margin   = 10,
-               .hsync_len      = 10,
-               .vsync_len      = 10,
-               .sync           = 0,
-               .vmode          = FB_VMODE_NONINTERLACED
-} } };
+struct display_info_t const displays[] = {
+       {
+               .bus    = -1,
+               .addr   = 0,
+               .pixfmt = IPU_PIX_FMT_RGB666,
+               .detect = NULL,
+               .enable = enable_lvds,
+               .mode   = {
+                       .name           = "Hannstar-XGA",
+                       .refresh        = 60,
+                       .xres           = 1024,
+                       .yres           = 768,
+                       .pixclock       = 15384,
+                       .left_margin    = 160,
+                       .right_margin   = 24,
+                       .upper_margin   = 29,
+                       .lower_margin   = 3,
+                       .hsync_len      = 136,
+                       .vsync_len      = 6,
+                       .sync           = FB_SYNC_EXT,
+                       .vmode          = FB_VMODE_NONINTERLACED
+               }
+       }, {
+               .bus    = -1,
+               .addr   = 0,
+               .pixfmt = IPU_PIX_FMT_RGB24,
+               .detect = detect_hdmi,
+               .enable = do_enable_hdmi,
+               .mode   = {
+                       .name           = "HDMI",
+                       .refresh        = 60,
+                       .xres           = 1024,
+                       .yres           = 768,
+                       .pixclock       = 15384,
+                       .left_margin    = 160,
+                       .right_margin   = 24,
+                       .upper_margin   = 29,
+                       .lower_margin   = 3,
+                       .hsync_len      = 136,
+                       .vsync_len      = 6,
+                       .sync           = FB_SYNC_EXT,
+                       .vmode          = FB_VMODE_NONINTERLACED
+               }
+       }, {
+               .bus    = 0,
+               .addr   = 0,
+               .pixfmt = IPU_PIX_FMT_RGB24,
+               .detect = NULL,
+               .enable = enable_rgb,
+               .mode   = {
+                       .name           = "SEIKO-WVGA",
+                       .refresh        = 60,
+                       .xres           = 800,
+                       .yres           = 480,
+                       .pixclock       = 29850,
+                       .left_margin    = 89,
+                       .right_margin   = 164,
+                       .upper_margin   = 23,
+                       .lower_margin   = 10,
+                       .hsync_len      = 10,
+                       .vsync_len      = 10,
+                       .sync           = 0,
+                       .vmode          = FB_VMODE_NONINTERLACED
+               }
+       }
+};
 size_t display_count = ARRAY_SIZE(displays);
 
 static void setup_display(void)
@@ -283,10 +287,10 @@ static void setup_display(void)
 
        /* set LDB0, LDB1 clk select to 011/011 */
        reg = readl(&mxc_ccm->cs2cdr);
-       reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
-                | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
-       reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
-             | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+       reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
+               MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+       reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
+               (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
        writel(reg, &mxc_ccm->cs2cdr);
 
        reg = readl(&mxc_ccm->cscmr2);
@@ -294,28 +298,28 @@ static void setup_display(void)
        writel(reg, &mxc_ccm->cscmr2);
 
        reg = readl(&mxc_ccm->chsccdr);
-       reg |= (CHSCCDR_CLK_SEL_LDB_DI0
-               << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
-       reg |= (CHSCCDR_CLK_SEL_LDB_DI0
-               << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
+       reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
+               MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+       reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
+               MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
        writel(reg, &mxc_ccm->chsccdr);
 
-       reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
-            | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
-            | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
-            | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
-            | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
-            | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
-            | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
-            | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
-            | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
+       reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
+               IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
+               IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+               IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
+               IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
+               IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+               IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
+               IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED |
+               IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
        writel(reg, &iomux->gpr[2]);
 
        reg = readl(&iomux->gpr[3]);
-       reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
-                       | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
-           | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
-              << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
+       reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
+               IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) |
+               (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+               IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
        writel(reg, &iomux->gpr[3]);
 }
 #endif /* CONFIG_VIDEO_IPUV3 */
@@ -538,6 +542,7 @@ int board_mmc_init(bd_t *bis)
 {
        struct src *psrc = (struct src *)SRC_BASE_ADDR;
        unsigned reg = readl(&psrc->sbmr1) >> 11;
+
        /*
         * Upon reading BOOT_CFG register the following map is done:
         * Bit 11 and 12 of BOOT_CFG register can determine the current
@@ -546,7 +551,6 @@ int board_mmc_init(bd_t *bis)
         * 0x2                  SD2
         * 0x3                  SD4
         */
-
        switch (reg & 0x3) {
        case 0x1:
                imx_iomux_v3_setup_multiple_pads(
@@ -836,6 +840,7 @@ void board_init_f(ulong dummy)
        arch_cpu_init();
 
        ccgr_init();
+
        gpr_init();
 
        /* iomux and setup of i2c */
-- 
1.9.1

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