This SoC has one gpio bank divided into two 32 bit registers, with a total of
52 GPIOs.
Signed-off-by: Álvaro Fernández Rojas <nolt...@gmail.com>
---
arch/mips/dts/brcm,bcm63268.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi
index 3d81047..3eda77d 100644
--- a/arch/mips/dts/brcm,bcm63268.dtsi
+++ b/arch/mips/dts/brcm,bcm63268.dtsi
@@ -63,6 +63,25 @@
mask = <0x1>;
};
+ gpio1: gpio-controller@100000c0 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x100000c0 0x4>, <0x100000c8 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <20>;
+
+ status = "disabled";
+ };
+
+ gpio0: gpio-controller@100000c4 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x100000c4 0x4>, <0x100000cc 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
uart0: serial@10000180 {
compatible = "brcm,bcm6345-uart";
reg = <0x10000180 0x18>;
--
2.1.4
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