Hi, On Wed, Apr 26, 2017 at 10:49:55PM +0800, Icenowy Zheng wrote: > This patchset contains several works on the sunxi DesignWare DRAM > controllers. > > The 1st patch made an option for H3-like DRAM controllers > (DesignWare ones), which can ease further import of alike controllers. > > The 2nd and 3rd patches are for supporting 16-bit DW DRAM controllers, > in order to add V3s DRAM support (The controller on V3s is 16-bit). > > The 4th patch adds bank detection code, in order to support some DDR2 > chips. > > The 5th patch adds a framework for select DRAM type and timing -- it's > needed for boards that use DRAM chips rather than DDR3. > > The 6th patch enables dual rank detection in the DW DRAM code on SoCs > except R40. For R40 the dual rank facility is still not so clear, so it's > temporarily disabled. > > The 7th~9th patches enables support for DRAM initialization and SPL for > the V3s SoC, which integrates a DDR2 chip. > > The 10th and 11th patches adds support for LPDDR3, with the stock boot0 > timing. (Seen in A83T boot0 source and some leaked H5/R40 libdram source) > > The 12th patches adds a defconfig for SoPine w/ official baseboard, which > utilizes LPDDR3.
All those changes looks good to me. I'll wait for Jens' review however, since he knows that part much more than I do. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
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