Add GEC2410 default config.
Signed-off-by: Hui.Tang <zetal...@gmail.com>
---
include/configs/gec2410.h | 275 +++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 275 insertions(+), 0 deletions(-)
create mode 100644 include/configs/gec2410.h
diff --git a/include/configs/gec2410.h b/include/configs/gec2410.h
new file mode 100644
index 0000000..98c8040
--- /dev/null
+++ b/include/configs/gec2410.h
@@ -0,0 +1,275 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroe...@sysgo.de>
+ * Gary Jennejohn <ga...@denx.de>
+ * David Mueller <d.muel...@elsoft.ch>
+ *
+ * Configuation settings for the GD-Embedded Software Center GEC2410 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
+#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
+#define CONFIG_GEC2410 1 /* on a GD-Embedded Software Center
GEC2410 Board */
+
+#define CONFIG_SYS_SDRAM_BASE 0x30000000
+
+/* input clock of PLL */
+#define CONFIG_SYS_CLK_FREQ 12000000/* the GEC2410 has 12MHz input clock */
+
+#if !defined(CONFIG_NAND_SPL) && (TEXT_BASE >= 0xc0000000)
+#define CONFIG_ENABLE_MMU
+#endif
+
+#define CONFIG_MEMORY_UPPER_CODE
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+
+#define USE_920T_MMU 1
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for
initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_CS8900 /* we have a CS8900 on-board */
+#define CONFIG_CS8900_BASE 0x19000300
+#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_S3C24X0_SERIAL 1
+#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on GEC2410 */
+
+/************************************************************
+ * RTC
+ ************************************************************/
+#define CONFIG_RTC_S3C24X0 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 115200
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_NAND
+#if defined(CONFIG_BOOT_ONENAND)
+#define CONFIG_CMD_ONENAND
+#endif
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+
+#define CONFIG_BOOTDELAY 3
+/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */
+#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.1.10
+#define CONFIG_SERVERIP 192.168.1.254
+/*#define CONFIG_BOOTFILE "elinos-lart" */
+/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial
port */
+/* what's this ? it's not used anywhere */
+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory
*/
+#define CONFIG_SYS_PROMPT "GEC2410#" /* Monitor Command
Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer
Size */
+#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size
*/
+#define CONFIG_SYS_MAXARGS 16 /* max number of
command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot
Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* memtest
works on */
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x3e00000) /*
62 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default load
address */
+
+/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
+/* it to wrap 100 times (total 1562500) to get 1 sec. */
+#define CONFIG_SYS_HZ 1562500
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE 0x40000 /* regular stack 256KB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1
*/
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+
+#define CONFIG_SYS_FLASH_BASE 0x00000000
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+
+#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks
*/
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one
chip */
+
+#define CONFIG_SYS_FLASH_CFI 1 /* Use CFI parameters (needed?)
*/
+/* Use drivers/cfi_flash.c, even though the flash is not CFI-compliant */
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_FLASH_CFI_LEGACY
+
+#define PHYS_FLASH_SIZE 0x00200000 /* 2MB */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /*
addr of environment */
+
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (5 * CONFIG_SYS_HZ) /* Timeout for
Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT (5 * CONFIG_SYS_HZ) /* Timeout for
Flash Write */
+
+#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment
Sector */
+
+/*
+ * GEC2410 board specific data
+ */
+
+#define CONFIG_IDENT_STRING " for GEC2410"
+
+/* base address for uboot */
+#define CONFIG_SYS_PHY_UBOOT_BASE (CONFIG_SYS_SDRAM_BASE + 0x03e00000)
+/* total memory available to uboot */
+#define CONFIG_SYS_UBOOT_SIZE (1024 * 1024)
+
+/* Put environment copies after the end of U-Boot owned RAM */
+#define CONFIG_NAND_ENV_DST (CONFIG_SYS_UBOOT_BASE + CONFIG_SYS_UBOOT_SIZE)
+
+#ifdef CONFIG_ENABLE_MMU
+#define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000
+#define CONFIG_BOOTCOMMAND "nand read 0xc0008000 0x60000 0x1a0000;" \
+ "bootm 0xc0008000"
+#else
+#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE
+#define CONFIG_BOOTCOMMAND "nand read 0x30008000 0x60000 0x1a0000;" \
+ "bootm 0x30008000"
+#endif
+
+/* NAND U-Boot load and start address */
+#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_MAPPED_RAM_BASE +
0x03e00000)
+
+#define CONFIG_ENV_OFFSET 0x0040000 /* Offset of Environment
Sector */
+
+/* NAND configuration */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x4e00000c /* NFDATA 0x4e00000c
R/W NAND Flash data register */
+/* #define CONFIG_SYS_S3C_NAND_HWECC */
+#define CONFIG_S3C2410_NAND_HWECC
+#define CONFIG_S3C2410_NAND_BBT
+
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_PHY_UBOOT_BASE /* NUB
load-addr */
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* NUB
start-addr */
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (4 * 1024) /* Offset to RAM U-Boot
image */
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (252 * 1024) /* Size of RAM U-Boot
image */
+
+/* NAND chip page size */
+#define CONFIG_SYS_NAND_PAGE_SIZE 512
+/* NAND chip block size */
+#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
+/* NAND chip page per block count */
+#define CONFIG_SYS_NAND_PAGE_COUNT 32
+/* Location of the bad-block label */
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+/* Extra address cycle for > 32MiB */
+#define CONFIG_SYS_NAND_4_ADDR_CYCLE 1 /* Fourth addr used
(>32MB) */
+
+
+/* Size of the block protected by one OOB (Spare Area in Samsung terminology)
*/
+#define CONFIG_SYS_NAND_ECCSIZE CONFIG_SYS_NAND_PAGE_SIZE
+/* Number of ECC bytes per OOB - S3C2410 calculates 4 bytes ECC in 1-bit mode
*/
+#define CONFIG_SYS_NAND_ECCBYTES 3
+/* Number of ECC-blocks per NAND page */
+#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE /
CONFIG_SYS_NAND_ECCSIZE)
+/* Size of a single OOB region */
+#define CONFIG_SYS_NAND_OOBSIZE 16
+/* Number of ECC bytes per page */
+#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES *
CONFIG_SYS_NAND_ECCSTEPS)
+/* ECC byte positions */
+#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2}
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
+/* Boot configuration (define only one of next 3) */
+#define CONFIG_BOOT_NAND
+
+#define CONFIG_NAND
+#define CONFIG_NAND_S3C2410 1
+
+/* Settings as above boot configuration */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_BOOTARGS "console=ttySAC,115200"
+
+#endif /* __CONFIG_H */
--
1.6.0.4
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