[U-Boot] [PATCH 3/5] rockchip: clk: rk3188: add ciu_clk entry for eMMC/SDMMC/SDIO

[Ziyuan Xu]

The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
it.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/clk/rockchip/clk_rk3188.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3188.c 
b/drivers/clk/rockchip/clk_rk3188.c
index d36cf8f..b32491d 100644
--- a/drivers/clk/rockchip/clk_rk3188.c
+++ b/drivers/clk/rockchip/clk_rk3188.c
@@ -269,14 +269,17 @@ static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, 
uint gclk_rate,
 
        switch (periph) {
        case HCLK_EMMC:
+       case SCLK_EMMC:
                con = readl(&cru->cru_clksel_con[12]);
                div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
                break;
        case HCLK_SDMMC:
+       case SCLK_SDMMC:
                con = readl(&cru->cru_clksel_con[11]);
                div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
                break;
        case HCLK_SDIO:
+       case SCLK_SDIO:
                con = readl(&cru->cru_clksel_con[12]);
                div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK;
                break;
@@ -298,16 +301,19 @@ static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, 
uint gclk_rate,
 
        switch (periph) {
        case HCLK_EMMC:
+       case SCLK_EMMC:
                rk_clrsetreg(&cru->cru_clksel_con[12],
                             EMMC_DIV_MASK << EMMC_DIV_SHIFT,
                             src_clk_div << EMMC_DIV_SHIFT);
                break;
        case HCLK_SDMMC:
+       case SCLK_SDMMC:
                rk_clrsetreg(&cru->cru_clksel_con[11],
                             MMC0_DIV_MASK << MMC0_DIV_SHIFT,
                             src_clk_div << MMC0_DIV_SHIFT);
                break;
        case HCLK_SDIO:
+       case SCLK_SDIO:
                rk_clrsetreg(&cru->cru_clksel_con[12],
                             SDIO_DIV_MASK << SDIO_DIV_SHIFT,
                             src_clk_div << SDIO_DIV_SHIFT);
@@ -466,6 +472,9 @@ static ulong rk3188_clk_get_rate(struct clk *clk)
        case HCLK_EMMC:
        case HCLK_SDMMC:
        case HCLK_SDIO:
+       case SCLK_EMMC:
+       case SCLK_SDMMC:
+       case SCLK_SDIO:
                new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ,
                                                clk->id);
                break;
@@ -505,6 +514,9 @@ static ulong rk3188_clk_set_rate(struct clk *clk, ulong 
rate)
        case HCLK_EMMC:
        case HCLK_SDMMC:
        case HCLK_SDIO:
+       case SCLK_EMMC:
+       case SCLK_SDMMC:
+       case SCLK_SDIO:
                new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ,
                                                clk->id, rate);
                break;
-- 
2.7.4


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