> -----Original Message-----
> From: york sun
> Sent: Saturday, March 25, 2017 10:30 PM
> To: Santan Kumar <santan.ku...@nxp.com>; u-boot@lists.denx.de
> Cc: Priyanka Jain <priyanka.j...@nxp.com>; Abhimanyu Saini
> <abhimanyu.sa...@nxp.com>
> Subject: Re: [PATCH 1/2][v3] armv8: ls2080a: Reorganise NAND_BOOT code
> in config flag
>
> On 03/02/2017 03:41 AM, Santan Kumar wrote:
> > Add CONFIG_NAND_BOOT config flag to organise NAND_BOOT specific
> code
> > in config flag like -nand-boot specfic errata errata_rcw_src()
> > -CONFIG_SYS_NAND_U_BOOT_DST,etc
> >
> > Signed-off-by: Santan Kumar <santan.ku...@nxp.com>
> > Signed-off-by: Priyanka Jain <priyanka.j...@nxp.com>
> > Signed-off-by: Abhimanyu Saini <abhimanyu.sa...@nxp.com>
> > ---
> > Changes for v3:
> > Rebased to latest codebase
> > Incorporated York's comments to defined CONFIG_NAND_BOOT in new
> line
> >
> > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +-
> > configs/ls2080aqds_nand_defconfig | 1 +
> > configs/ls2080ardb_nand_defconfig | 1 +
> > include/configs/ls2080a_common.h | 5 +++++
> > include/configs/ls2080aqds.h | 4 +++-
> > 5 files changed, 11 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > index 9489f85..fa68baf 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > @@ -134,7 +134,7 @@ void erratum_a009635(void)
> >
> > static void erratum_rcw_src(void)
> > {
> > -#if defined(CONFIG_SPL)
> > +#if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
> > u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
> > u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
> > u32 val;
> > diff --git a/configs/ls2080aqds_nand_defconfig
> > b/configs/ls2080aqds_nand_defconfig
> > index 8910938..bc0b9b1 100644
> > --- a/configs/ls2080aqds_nand_defconfig
> > +++ b/configs/ls2080aqds_nand_defconfig
> > @@ -12,6 +12,7 @@ CONFIG_FIT=y
> > CONFIG_FIT_VERBOSE=y
> > CONFIG_OF_BOARD_SETUP=y
> > CONFIG_OF_STDOUT_VIA_ALIAS=y
> > +CONFIG_NAND_BOOT=y
> > CONFIG_SYS_EXTRA_OPTIONS="NAND, LS2080A"
> > CONFIG_BOOTDELAY=10
> > CONFIG_SPL=y
> > diff --git a/configs/ls2080ardb_nand_defconfig
> > b/configs/ls2080ardb_nand_defconfig
> > index 8223111..d449190 100644
> > --- a/configs/ls2080ardb_nand_defconfig
> > +++ b/configs/ls2080ardb_nand_defconfig
> > @@ -12,6 +12,7 @@ CONFIG_FIT=y
> > CONFIG_FIT_VERBOSE=y
> > CONFIG_OF_BOARD_SETUP=y
> > CONFIG_OF_STDOUT_VIA_ALIAS=y
> > +CONFIG_NAND_BOOT=y
> > CONFIG_SYS_EXTRA_OPTIONS="NAND, LS2080A"
> > CONFIG_BOOTDELAY=10
> > CONFIG_SPL=y
> > diff --git a/include/configs/ls2080a_common.h
> > b/include/configs/ls2080a_common.h
> > index 4173d9a..ae72939 100644
> > --- a/include/configs/ls2080a_common.h
> > +++ b/include/configs/ls2080a_common.h
> > @@ -216,6 +216,7 @@ unsigned long long get_qixis_addr(void);
> >
> > #define CONFIG_PANIC_HANG /* do not reset board on panic */
> >
> > +#ifdef CONFIG_SPL
>
> Why this?
[Santan Kumar] yes we don't required this I will remove it.
>
> > #define CONFIG_SPL_BSS_START_ADDR 0x80100000
> > #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
> > #define CONFIG_SPL_FRAMEWORK
> > @@ -225,11 +226,15 @@ unsigned long long get_qixis_addr(void);
> > #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
> > #define CONFIG_SPL_TEXT_BASE 0x1800a000
> >
> > +#ifdef CONFIG_NAND_BOOT
> > +#define CONFIG_SPL_NAND_SUPPORT
>
> This is a Kconfig option. Please select it properly.
[Santan Kumar] I will remove it since it is there in kconfig.
>
> > #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
> > #define CONFIG_SYS_NAND_U_BOOT_START
> CONFIG_SYS_NAND_U_BOOT_DST
> > +#endif
> > #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
> > #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
> > #define CONFIG_SYS_MONITOR_LEN (640 * 1024)
> > +#endif
> >
> > #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip
> size */
> >
> > diff --git a/include/configs/ls2080aqds.h
> > b/include/configs/ls2080aqds.h index 08d1586..93f6b51 100644
> > --- a/include/configs/ls2080aqds.h
> > +++ b/include/configs/ls2080aqds.h
> > @@ -197,7 +197,8 @@ unsigned long get_board_ddr_clk(void);
> > FTIM2_GPCM_TWP(0x3E))
> > #define CONFIG_SYS_CS3_FTIM3 0x0
> >
> > -#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
> > +#if defined(CONFIG_SPL)
> > +#if defined(CONFIG_NAND_BOOT)
> > #define CONFIG_SYS_CSPR1_EXT
> CONFIG_SYS_NOR0_CSPR_EXT
> > #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
> > #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
> > @@ -233,6 +234,7 @@ unsigned long get_board_ddr_clk(void);
> > #define CONFIG_SPL_PAD_TO 0x20000
> > #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
> > #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
> > +#endif
> > #else
> > #define CONFIG_SYS_CSPR0_EXT
> CONFIG_SYS_NOR0_CSPR_EXT
> > #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
> >
>
> Since you are reorganizing NAND boot, can you comb through all Layerscape
> NAND boot and make them consistent in the sense of location in RAM,
> malloc space, etc.? Or even better, can you also take SD boot and make them
> consistent? I would like to see the RAM version at the same location, with
> plenty of space ahead of it (may be used for falcon boot).
>
> York
[Santan Kumar] : To do this I need to have more understanding about the code. I
will analyze this in detail and send a separate patch later. Is it fine?
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