On 03/24/2017 02:58 AM, Stephen Arnold wrote: > This patch adds the steps to manually (re)build a Quartus FPGA project, > generate the required BSP glue, and update u-boot handoff files for > mainline SPL support. Requires Quartus toolchain and current U-Boot. > > Signed-off-by: Steve Arnold <stephen.arnol...@gmail.com> > Cc: Dinh Nguyen <dingu...@kernel.org> > Cc: Stefan Roese <s...@denx.de> > Cc: Marek Vasut <ma...@denx.de> > --- > Changes for v2: > - Addressed comments by marex > - Added some clarification > - Made formatting a bit more rst-ish > > doc/README.socfpga | 141 > +++++++++++++++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 136 insertions(+), 5 deletions(-) > > diff --git a/doc/README.socfpga b/doc/README.socfpga > index cb805cfd3a..cae0ef1a21 100644 > --- a/doc/README.socfpga > +++ b/doc/README.socfpga > @@ -1,18 +1,149 @@ > - > --------------------------------------------- > +---------------------------------------- > SOCFPGA Documentation for U-Boot and SPL > --------------------------------------------- > +---------------------------------------- > > This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore > based SOCFPGA. To know more about the hardware itself, please refer to > www.altera.com. > > > --------------------------------------------- > socfpga_dw_mmc > --------------------------------------------- > +-------------- > + > Here are macro and detailed configuration required to enable DesignWare SDMMC > controller support within SOCFPGA > > #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 > -> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM > + > +-------------------------------------------------- > +Generating the handoff header files for U-Boot SPL > +-------------------------------------------------- > + > +This text is assuming quartus 16.1, but newer versions will probably work > just fine too; > +verified with DE1_SOC_Linux_FB demo project > (https://github.com/VCTLabs/DE1_SOC_Linux_FB). > +Updated/working projects should build using either process below. > + > +Note: it *should* work from Quartus 14.0.200 onwards, however, the current > vendor demo > +projects must have the IP cores updated as shown below. > + > +Rebuilding your Quartus project > +------------------------------- > + > +Choose one of the follwing methods, either command line or GUI. > + > +Using the comaand line > +~~~~~~~~~~~~~~~~~~~~~~ > + > +First run the embedded command shell, using your path to the Quartus install: > + > + $ /path/to/intelFPGA/16.1/embedded/embedded_command_shell.sh > + > +Then (if necessary) update the IP cores in the project, generate HDL code, > and > +build the project: > + > + $ cd path/to/project/dir > + $ qsys-generate soc_system.qsys --upgrade-ip-cores > + $ qsys-generate soc_system.qsys --synthesis=[VERILOG|VHDL] > + $ quartus_sh --flow compile <project name> > + > +Convert the resulting .sof file (SRAM object file) to .rbf file (Raw bit > file): > + > + $ quartus_cpf -c <project_name>.sof soc_system.rbf > + > + > +Generate BSP handoff files > +~~~~~~~~~~~~~~~~~~~~~~~~~~ > + > +You can run the bsp editor GUI below, or run the following command from the > +project directory: > + > + $ /path/to/bsb/tools/bsp-create-settings --type spl --bsp-dir build \ > + --preloader-settings-dir hps_isw_handoff/soc_system_hps_0/ \ > + --settings build/settings.bsp > + > +You should use the bsp "build" directory above (ie, where the settings.bsp > file is) > +in the following u-boot command to update the board headers. Once these > headers > +are updated for a given project build, u-boot should be configured for the > +project board (eg, de0-nano-sockit) and then build the normal spl build. ^^^ just soc , not sockit .
Fixed and applied, thanks! -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
