On Mon, Feb 27, 2017 at 3:02 AM, Rask Ingemann Lambertsen <r...@formelder.dk> wrote: > This patch uses the AXP808 support to raise the Cortex-A7 core voltage > from the power-on default of 0.9 V to 1.02 V and increases the clock > frequency from the default 1008 MHz to 1200 MHz. This is the maximum clock > frequency listed in the vendor's sys_config.fex file.
This should really be left to a proper cpufreq/DVFS system. The bootloader should bring up the system in a safe, usable state. 1008 MHz is the default across all Allwinner SoCs, aside from a few boards that cannot reach it without overvoltage. It's even the default in BSP bootloaders. ChenYu > > Signed-off-by: Rask Ingemann Lambertsen <r...@formelder.dk> > --- > This patch goes on top of "ARM: sunxi: Add defconfig for Sunchip CX-A99". > > FWIW, I seem to get away with > > CONFIG_SYS_CLK_FREQ=1296000000 > CONFIG_AXP_DCDCA_VOLT=1100 > > but neither "Allwinner UltraOcta A80 Datasheet" (revision 1.3) nor > "Allwinner A80 User Manual" (revision 1.3.1) say anything about the > supported clock frequencies. > > configs/Sunchip_CX-A99_defconfig | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/configs/Sunchip_CX-A99_defconfig > b/configs/Sunchip_CX-A99_defconfig > index 7530d7d..3b760d8 100644 > --- a/configs/Sunchip_CX-A99_defconfig > +++ b/configs/Sunchip_CX-A99_defconfig > @@ -4,6 +4,7 @@ CONFIG_MACH_SUN9I=y > CONFIG_DRAM_CLK=600 > CONFIG_DRAM_ZQ=3881915 > CONFIG_DRAM_ODT_EN=y > +CONFIG_SYS_CLK_FREQ=1200000000 > CONFIG_MMC0_CD_PIN="PH17" > CONFIG_MMC_SUNXI_SLOT_EXTRA=2 > CONFIG_USB0_VBUS_PIN="PH15" > @@ -17,6 +18,7 @@ CONFIG_SPL=y > # CONFIG_CMD_IMLS is not set > # CONFIG_CMD_FLASH is not set > # CONFIG_CMD_FPGA is not set > +CONFIG_AXP_DCDCA_VOLT=1020 > # CONFIG_SPL_DOS_PARTITION is not set > # CONFIG_SPL_ISO_PARTITION is not set > # CONFIG_SPL_EFI_PARTITION is not set > -- > 2.10.2 > _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
