Hi Andy,
On Tue, Feb 14, 2017 at 10:47 PM, Andy Shevchenko
<andriy.shevche...@linux.intel.com> wrote:
> There is no microcode update available for SoCs used on Intel MID
> platforms.
>
> Use conditional to bypass it.
>
> Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
> ---
> arch/x86/cpu/mp_init.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
> index 988073cc79..4e2f000f75 100644
> --- a/arch/x86/cpu/mp_init.c
> +++ b/arch/x86/cpu/mp_init.c
> @@ -248,7 +248,7 @@ static int load_sipi_vector(atomic_t **ap_countp, int
> num_cpus)
> if (!stack)
> return -ENOMEM;
> params->stack_top = (u32)(stack + size);
> -#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP)
> +#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) &&
> !defined(CONFIG_INTEL_MID)
> params->microcode_ptr = ucode_base;
> debug("Microcode at %x\n", params->microcode_ptr);
> #endif
Is this patch necessary? If Intel MID does not define CONFIG_QEMU or
CONFIG_HAVE_FSP, current logic should work.
Regards,
Bin
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