Before disable cache, need to first flush cache.
There maybe dirty data in D-Cache before disable D-Cache.
After disable D-Cache, the first store instructions in
psci_v7_flush_dcache_all will directly store registers
{r4-r5, r7, r9-r11, lr} to memory.
If there is dirty data before disable D-Cache,
psci_v7_flush_dcache_all will flush data to memory,
and may overwrite the memory that hold the registers
{r4-r5, r7, r9-r11, lr}.
So before disable cache, first flush D-Cache.
Signed-off-by: Peng Fan <peng....@nxp.com>
Cc: Albert Aribaud <albert.u.b...@aribaud.net>
Cc: Chen-Yu Tsai <w...@csie.org>
Cc: Hans de Goede <hdego...@redhat.com>
Cc: Hongbo Zhang <hongbo.zh...@nxp.com>
Cc: York Sun <york....@nxp.com>
Cc: Marc Zyngier <marc.zyng...@arm.com>
Cc: Tom Rini <tr...@konsulko.com>
---
arch/arm/cpu/armv7/psci.S | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 6a36208..95b962d 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -258,6 +258,10 @@ ENDPROC(psci_enable_smp)
ENTRY(psci_cpu_off_common)
push {lr}
+ bl psci_v7_flush_dcache_all
+
+ clrex @ Why???
+
mrc p15, 0, r0, c1, c0, 0 @ SCTLR
bic r0, r0, #(1 << 2) @ Clear C bit
mcr p15, 0, r0, c1, c0, 0 @ SCTLR
--
2.6.2
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