To enable access to the slave CP its memory needs to be added to the
MMU memory map.

Signed-off-by: Stefan Roese <s...@denx.de>
Cc: Nadav Haklai <nad...@marvell.com>
Cc: Neta Zur Hershkovits <n...@marvell.com>
Cc: Kostya Porotchkin <kos...@marvell.com>
Cc: Omri Itach <om...@marvell.com>
Cc: Igal Liberman <ig...@marvell.com>
Cc: Haim Boot <ha...@marvell.com>
Cc: Hanna Hawa <han...@marvell.com>
---
 arch/arm/mach-mvebu/armada8k/cpu.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c 
b/arch/arm/mach-mvebu/armada8k/cpu.c
index 036430c..f8e69d6 100644
--- a/arch/arm/mach-mvebu/armada8k/cpu.c
+++ b/arch/arm/mach-mvebu/armada8k/cpu.c
@@ -39,7 +39,7 @@ static struct mm_region mvebu_mem_map[] = {
                         PTE_BLOCK_NON_SHARE
        },
        {
-               /* SRAM, MMIO regions - CP110 region */
+               /* SRAM, MMIO regions - CP110 master region */
                .phys = 0xf2000000UL,
                .virt = 0xf2000000UL,
                .size = 0x02000000UL,   /* 32MiB internal registers */
@@ -47,6 +47,14 @@ static struct mm_region mvebu_mem_map[] = {
                         PTE_BLOCK_NON_SHARE
        },
        {
+               /* SRAM, MMIO regions - CP110 slave region */
+               .phys = 0xf4000000UL,
+               .virt = 0xf4000000UL,
+               .size = 0x02000000UL,   /* 32MiB internal registers */
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE
+       },
+       {
                /* List terminator */
                0,
        }
-- 
2.10.2

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