Thanks Marek, On 10/30/2016 01:03 PM, Marek Vasut wrote: > On 10/30/2016 08:20 PM, Eric Nelson wrote: >> The DDR calibration routines are gated by conditionals for the >> i.MX6DQ SOCs, but with the use of the sysinfo parameter, these >> are usable on at least i.MX6SDL and i.MX6SL variants with DDR3. >> >> Also, since only the Novena board currently uses the dynamic >> DDR calibration routines, these routines waste space on other >> boards using SPL. >> >> Add a KConfig entry to allow boards to selectively include the >> DDR calibration routines. >> >> Signed-off-by: Eric Nelson <e...@nelint.com> >> --- >> arch/arm/cpu/armv7/mx6/Kconfig | 5 +++++ >> arch/arm/cpu/armv7/mx6/ddr.c | 3 +-- >> arch/arm/include/asm/arch-mx6/mx6-ddr.h | 2 +- >> configs/novena_defconfig | 1 + >> 4 files changed, 8 insertions(+), 3 deletions(-) >> >> diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig >> index 762a581..32536c0 100644 >> --- a/arch/arm/cpu/armv7/mx6/Kconfig >> +++ b/arch/arm/cpu/armv7/mx6/Kconfig >> @@ -35,6 +35,11 @@ config MX6ULL >> bool >> select MX6UL >> >> +config MX6_DDRCAL >> + bool "Include dynamic DDR calibration routines" >> + depends on SPL >> + default n > > Help text would really be helpful ;) >
Cool. I'll fix this and re-send the series as V2 (with the fourth patch). _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
