From: Stephen Warren <swar...@nvidia.com>
ARM CPUs can architecturally (speculatively) prefetch completely arbitrary
normal memory locations, as defined by the current translation tables. The
current MMU configuration for 64-bit Tegras maps an extremely large range
of addresses as DRAM, well beyond the actual physical maximum DRAM window,
even though U-Boot only needs access to the first 2GB of DRAM; the Tegra
port of U-Boot deliberately limits itself to 2GB of RAM since some HW
modules on at least some 64-bit Tegra SoCs can only access a 32-bit
physical address space. This change reduces the amount of RAM mapped via
the MMU to disallow the CPU from ever speculatively accessing RAM that
U-Boot will definitely not access. This avoids the possibility of the HW
raising SError due to accesses to always-invalid physical addresses.
Signed-off-by: Stephen Warren <swar...@nvidia.com>
---
arch/arm/mach-tegra/arm64-mmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c
index 7b1d258ed84f..a79a5192e076 100644
--- a/arch/arm/mach-tegra/arm64-mmu.c
+++ b/arch/arm/mach-tegra/arm64-mmu.c
@@ -23,7 +23,7 @@ static struct mm_region tegra_mem_map[] = {
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
- .size = 0xff80000000UL,
+ .size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
--
2.10.1
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