Adds a command 440epx_r to dump over 140 internal register which
define the HW configuration. Command name shortened from
440epx_regdump to 440epx_r to align nicely with the help command.
Handy for documentation and verifying changes.
Signed-off-by: Niklaus Giger <niklaus.gi...@netstal.com>
---
cpu/ppc4xx/440epx_regdump.c | 282 +++++++++++++++++++++++++++++++++++++++++++
cpu/ppc4xx/Makefile | 4 +
2 files changed, 286 insertions(+), 0 deletions(-)
create mode 100644 cpu/ppc4xx/440epx_regdump.c
diff --git a/cpu/ppc4xx/440epx_regdump.c b/cpu/ppc4xx/440epx_regdump.c
new file mode 100644
index 0000000..0e0478d
--- /dev/null
+++ b/cpu/ppc4xx/440epx_regdump.c
@@ -0,0 +1,282 @@
+/*
+ *(C) Copyright 2005-2009 Netstal Maschinen AG
+ * Bruno Hars (bruno.h...@netstal.com)
+ *
+ * This source code is free software; you can redistribute it
+ * and/or modify it in source code form under the terms of the GNU
+ * General Public License as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+/*
+ * cmd_440epx_regdump.c - CPU Register Dump for HCU5 board with PPC440EPx
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+
+enum REGISTER_TYPE {
+ DCR, /* Directly Accessed DCR's */
+ IDCR1, /* Indirectly Accessed DCR via SDRAM0_CFGADDR/SDRAM0_CFGDATA */
+ IDCR2, /* Indirectly Accessed DCR via EBC0_CFGADDR/EBC0_CFGDATA */
+ IDCR3, /* Indirectly Accessed DCR via EBM0_CFGADDR/EBM0_CFGDATA */
+ IDCR4, /* Indirectly Accessed DCR via PPM0_CFGADDR/PPM0_CFGDATA */
+ IDCR5, /* Indirectly Accessed DCR via CPR0_CFGADDR/CPR0_CFGDATA */
+ IDCR6, /* Indirectly Accessed DCR via SDR0_CFGADDR/SDR0_CFGDATA */
+ MM /* Directly Accessed MMIO Register */
+};
+
+struct cpu_register {
+ char *name;
+ enum REGISTER_TYPE type;
+ u32 address;
+};
+
+/*
+ * PPC440EPx registers ordered for output
+ * name type addr size
+ * -------------------------------------------
+ */
+const struct cpu_register ppc440epx_reg[] = {
+ {"EBC0_B0CR", IDCR2, PB0CR},
+ {"EBC0_B1CR", IDCR2, PB1CR},
+ {"EBC0_B2CR", IDCR2, PB2CR},
+ {"EBC0_B3CR", IDCR2, PB3CR},
+ {"EBC0_B4CR", IDCR2, PB4CR},
+ {"EBC0_B5CR", IDCR2, PB5CR},
+ {"EBC0_B0AP", IDCR2, PB0AP},
+ {"EBC0_B1AP", IDCR2, PB1AP},
+ {"EBC0_B2AP", IDCR2, PB2AP},
+ {"EBC0_B3AP", IDCR2, PB3AP},
+ {"EBC0_B4AP", IDCR2, PB4AP},
+ {"EBC0_B5AP", IDCR2, PB5AP},
+ {"EBC0_CFG", IDCR2, 0x23},
+ {"SDR0_SDSTP0", IDCR6, SDR0_SDSTP0},
+ {"SDR0_SDSTP1", IDCR6, SDR0_SDSTP1},
+ {"SDR0_SDSTP2", IDCR6, 0x4001},
+ {"SDR0_SDSTP3", IDCR6, 0x4003},
+ {"SDR0_CUST0", IDCR6, SDR0_CUST0},
+ {"SDR0_CUST1", IDCR6, SDR0_CUST1},
+ {"SDR0_EBC0", IDCR6, 0x0100},
+ {"SDR0_AMP0", IDCR6, 0x0240},
+ {"SDR0_AMP1", IDCR6, 0x0241},
+ {"SDR0_CP440", IDCR6, SDR0_CP440},
+ {"SDR0_CRYP0", IDCR6, 0x4500},
+ {"SDR0_DDRCFG", IDCR6, 0x00E0},
+ {"SDR0_EMAC0RXST", IDCR6, 0x4301},
+ {"SDR0_EMAC0TXST", IDCR6, 0x4302},
+ {"SDR0_MFR", IDCR6, SDR0_MFR},
+ {"SDR0_PCI0", IDCR6, SDR0_PCI0},
+ {"SDR0_PFC0", IDCR6, SDR0_PFC0},
+ {"SDR0_PFC1", IDCR6, SDR0_PFC1},
+ {"SDR0_PFC2", IDCR6, SDR0_PFC2},
+ {"SDR0_PFC4", IDCR6, SDR0_PFC4},
+ {"SDR0_UART0", IDCR6, SDR0_UART0},
+ {"SDR0_UART1", IDCR6, SDR0_UART1},
+ {"SDR0_UART2", IDCR6, SDR0_UART2},
+ {"SDR0_UART3", IDCR6, SDR0_UART3},
+ {"DDR0_02", IDCR1, 2},
+ {"DDR0_00", IDCR1, 0},
+ {"DDR0_01", IDCR1, 1},
+ {"DDR0_03", IDCR1, 3},
+ {"DDR0_04", IDCR1, 4},
+ {"DDR0_05", IDCR1, 5},
+ {"DDR0_06", IDCR1, 6},
+ {"DDR0_07", IDCR1, 7},
+ {"DDR0_08", IDCR1, 8},
+ {"DDR0_09", IDCR1, 9},
+ {"DDR0_10", IDCR1, 10},
+ {"DDR0_11", IDCR1, 11},
+ {"DDR0_12", IDCR1, 12},
+ {"DDR0_14", IDCR1, 14},
+ {"DDR0_17", IDCR1, 17},
+ {"DDR0_18", IDCR1, 18},
+ {"DDR0_19", IDCR1, 19},
+ {"DDR0_20", IDCR1, 20},
+ {"DDR0_21", IDCR1, 21},
+ {"DDR0_22", IDCR1, 22},
+ {"DDR0_23", IDCR1, 23},
+ {"DDR0_24", IDCR1, 24},
+ {"DDR0_25", IDCR1, 25},
+ {"DDR0_26", IDCR1, 26},
+ {"DDR0_27", IDCR1, 27},
+ {"DDR0_28", IDCR1, 28},
+ {"DDR0_31", IDCR1, 31},
+ {"DDR0_32", IDCR1, 32},
+ {"DDR0_33", IDCR1, 33},
+ {"DDR0_34", IDCR1, 34},
+ {"DDR0_35", IDCR1, 35},
+ {"DDR0_36", IDCR1, 36},
+ {"DDR0_37", IDCR1, 37},
+ {"DDR0_38", IDCR1, 38},
+ {"DDR0_39", IDCR1, 39},
+ {"DDR0_40", IDCR1, 40},
+ {"DDR0_41", IDCR1, 41},
+ {"DDR0_42", IDCR1, 42},
+ {"DDR0_43", IDCR1, 43},
+ {"DDR0_44", IDCR1, 44},
+ {"CPM0_ER", DCR, 0x0B0},
+ {"CPM1_ER", DCR, 0x0F0},
+ {"CPR0_ICFG", IDCR5, CPR0_ICFG},
+ {"CPR0_MALD", IDCR5, CPR0_MALD},
+ {"CPR0_OPBD0", IDCR5, 0x00C0},
+ {"CPR0_PERD0", IDCR5, 0x00E0},
+ {"CPR0_PLLC0", IDCR5, 0x0040},
+ {"CPR0_PLLD0", IDCR5, 0x0060},
+ {"CPR0_PRIMAD0", IDCR5, 0x0080},
+ {"CPR0_PRIMBD0", IDCR5, 0x00A0},
+ {"CPR0_SPCID", IDCR5, 0x0120},
+ {"SPI0_MODE", MM, 0xEF600900},
+ {"IIC0_CLKDIV", MM, 0xEF60070C},
+ {"PCIL0_PMM0MA", MM, 0xEF400004},
+ {"PCIL0_PMM1MA", MM, 0xEF400014},
+ {"PCIL0_PTM1LA", MM, 0xEF400034},
+ {"PCIL0_PTM1MS", MM, 0xEF400030},
+ {"PCIL0_PTM2LA", MM, 0xEF40003C},
+ {"PCIL0_PTM2MS", MM, 0xEF400038},
+ {"MAL0_CFG", DCR, MAL0_CFG},
+ {"ZMII0_FER", MM, 0xEF600D00},
+ {"ZMII0_SSR", MM, 0xEF600D04},
+ {"EMAC0_IPGVR", MM, 0xEF600E58},
+ {"EMAC0_MR1", MM, 0xEF600E04},
+ {"EMAC0_PTR", MM, 0xEF600E2C},
+ {"EMAC0_RWMR", MM, 0xEF600E64},
+ {"EMAC0_STACR", MM, 0xEF600E5C},
+ {"EMAC0_TMR0", MM, 0xEF600E08},
+ {"EMAC0_TMR1", MM, 0xEF600E0C},
+ {"EMAC0_TRTR", MM, 0xEF600E60},
+ {"EMAC1_MR1", MM, 0xEF600F04},
+ {"GPIO0_OR", MM, GPIO0_OR},
+ {"GPIO1_OR", MM, GPIO1_OR},
+ {"GPIO0_TCR", MM, GPIO0_TCR},
+ {"GPIO1_TCR", MM, GPIO1_TCR},
+ {"GPIO0_ODR", MM, GPIO0_ODR},
+ {"GPIO1_ODR", MM, GPIO1_ODR},
+ {"GPIO0_OSRL", MM, GPIO0_OSRL},
+ {"GPIO0_OSRH", MM, GPIO0_OSRH},
+ {"GPIO1_OSRL", MM, GPIO1_OSRL},
+ {"GPIO1_OSRH", MM, GPIO1_OSRH},
+ {"GPIO0_TSRL", MM, GPIO0_TSRL},
+ {"GPIO0_TSRH", MM, GPIO0_TSRH},
+ {"GPIO1_TSRL", MM, GPIO1_TSRL},
+ {"GPIO1_TSRH", MM, GPIO1_TSRH},
+ {"GPIO0_IR", MM, GPIO0_IR},
+ {"GPIO1_IR", MM, GPIO1_IR},
+ {"GPIO0_ISR1L", MM, GPIO0_ISR1L},
+ {"GPIO0_ISR1H", MM, GPIO0_ISR1H},
+ {"GPIO1_ISR1L", MM, GPIO1_ISR1L},
+ {"GPIO1_ISR1H", MM, GPIO1_ISR1H},
+ {"GPIO0_ISR2L", MM, GPIO0_ISR2L},
+ {"GPIO0_ISR2H", MM, GPIO0_ISR2H},
+ {"GPIO1_ISR2L", MM, GPIO1_ISR2L},
+ {"GPIO1_ISR2H", MM, GPIO1_ISR2H},
+ {"GPIO0_ISR3L", MM, GPIO0_ISR3L},
+ {"GPIO0_ISR3H", MM, GPIO0_ISR3H},
+ {"GPIO1_ISR3L", MM, GPIO1_ISR3L},
+ {"GPIO1_ISR3H", MM, GPIO1_ISR3H},
+ {"SDR0_USB2PHY0CR", IDCR6, SDR0_USB2PHY0CR},
+ {"SDR0_USB2H0CR", IDCR6, SDR0_USB2H0CR},
+ {"SDR0_USB2D0CR", IDCR6, SDR0_USB2D0CR},
+ {"PLB4A0_ACR", DCR, 0x081},
+ {"PLB4A1_ACR", DCR, 0x089},
+ {"PLB3A0_ACR", DCR, 0x077},
+ {"OPB2PLB40_BCTRL", DCR, 0x350},
+ {"P4P3BO0_CFG", DCR, 0x026}
+};
+
+/*
+ * CPU Register dump of PPC440EPx
+ * Output in order of struct ppc440epx_reg
+ */
+int do_440epx_regdump (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned int i;
+ unsigned int n;
+ u32 value;
+ enum REGISTER_TYPE type;
+
+ printf
+ ("\nDump PPC440EPx HW configuration registers\n\n");
+ n = sizeof (ppc440epx_reg) / sizeof (ppc440epx_reg[0]);
+ for (i = 0; i < n; i++) {
+ value = 0;
+ type = ppc440epx_reg[i].type;
+ switch (type) {
+ case DCR: /* Directly Accessed DCR's */
+ switch (ppc440epx_reg[i].address) {
+ case 0x00b0:
+ value = mfdcr ( 0x00b0 );
+ break;
+ case 0x00f0:
+ value = mfdcr ( 0x00f0 );
+ break;
+ case 0x0180:
+ value = mfdcr ( 0x0180 );
+ break;
+ case 0x0081:
+ value = mfdcr ( 0x0081 );
+ break;
+ case 0x0089:
+ value = mfdcr ( 0x0089 );
+ break;
+ case 0x0077:
+ value = mfdcr ( 0x0077 );
+ break;
+ case 0x0350:
+ value = mfdcr ( 0x0350 );
+ break;
+ case 0x0026:
+ value = mfdcr ( 0x0026 );
+ break;
+ default:
+ printf ("\nERROR: unknown DCR address: 0x%x\n",
+ ppc440epx_reg[i].address);
+ break;
+ }
+ break;
+ case IDCR1: /* Indirect via SDRAM0_CFGADDR/DDR0_CFGDATA */
+ mtdcr (SDRAM0_CFGADDR, ppc440epx_reg[i].address);
+ value = mfdcr (SDRAM0_CFGDATA);
+ break;
+ case IDCR2: /* Indirect via EBC0_CFGADDR/EBC0_CFGDATA */
+ mtdcr (EBC0_CFGADDR, ppc440epx_reg[i].address);
+ value = mfdcr (EBC0_CFGDATA);
+ break;
+ case IDCR5: /* Indirect via CPR0_CFGADDR/CPR0_CFGDATA */
+ mtdcr (CPR0_CFGADDR, ppc440epx_reg[i].address);
+ value = mfdcr (CPR0_CFGDATA);
+ break;
+ case IDCR6: /* Indirect via SDR0_CFGADDR/SDR0_CFGDATA */
+ mtdcr (SDR0_CFGADDR, ppc440epx_reg[i].address);
+ value = mfdcr (SDR0_CFGDATA);
+ break;
+ case MM: /* Directly Accessed MMIO Register */
+ value = *(volatile unsigned long*)
ppc440epx_reg[i].address;
+ break;
+ default:
+ printf
+ ("\nERROR: struct entry %d: unknown register
type\n",
+ i);
+ break;
+ }
+ printf ("0x%08x %-16s: 0x%08x\n", ppc440epx_reg[i].address,
+ ppc440epx_reg[i].name, value);
+ }
+ return 0;
+}
+
+/* define do_440epx_regdump as u-boot command */
+U_BOOT_CMD (440epx_r, 2, 1, do_440epx_regdump,
+ "print register information for PPC440EPX processor",
+ "");
diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile
index 2050b17..2d623a9 100644
--- a/cpu/ppc4xx/Makefile
+++ b/cpu/ppc4xx/Makefile
@@ -33,6 +33,10 @@ SOBJS += dcr.o
SOBJS += kgdb.o
COBJS := 40x_spd_sdram.o
+ifdef CONFIG_440EPX
+COBJS += 440epx_regdump.o
+endif
+
COBJS += 44x_spd_ddr.o
COBJS += 44x_spd_ddr2.o
ifdef CONFIG_PPC4xx_DDR_AUTOCALIBRATION
--
1.6.3.3
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