Dear Kumar Gala,
In message <1253380099-27864-7-git-send-email-ga...@kernel.crashing.org> you
wrote:
> The means to determine the core, bus, and DDR frequencies are completely
> new on CoreNet style platforms. Additionally on p4080 we can have
> different frequencies for FMAN and PME IP blocks. We need to keep track
> of the FMAN & PME frequencies since they are used for time stamping
> capabilities inside each block.
>
> Signed-off-by: Kumar Gala <ga...@kernel.crashing.org>
> ---
> cpu/mpc85xx/cpu.c | 29 +++++++++++++++++
> cpu/mpc85xx/speed.c | 85
> +++++++++++++++++++++++++++++++++++++++++++++++++++
> include/e500.h | 6 +++
> 3 files changed, 120 insertions(+), 0 deletions(-)
>
> diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
> index 25c0416..1c0f2b2 100644
> --- a/cpu/mpc85xx/cpu.c
> +++ b/cpu/mpc85xx/cpu.c
> @@ -46,11 +46,20 @@ int checkcpu (void)
> char buf1[32], buf2[32];
> #ifdef CONFIG_DDR_CLK_FREQ
> volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> +#ifdef CONFIG_FSL_CORENET
> + u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
> + >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
> +#else
> u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
> >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
> +#endif
> +#else
> +#ifdef CONFIG_FSL_CORENET
> + u32 ddr_sync = 0;
> #else
> u32 ddr_ratio = 0;
> #endif
> +#endif
Please make this
#endif /* CONFIG_DDR_CLK_FREQ */
so we can see more easily what ends wher ein this #ifdef hell.
> +#ifdef CONFIG_FSL_CORENET
> + if (ddr_sync == 1)
> + printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous),
> ",
> + strmhz(buf1, sysinfo.freqDDRBus/2),
> + strmhz(buf2, sysinfo.freqDDRBus));
> + else
> + printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous),
> ",
> + strmhz(buf1, sysinfo.freqDDRBus/2),
> + strmhz(buf2, sysinfo.freqDDRBus));
Please use braces around multi-line statements.
...
> + rcw_tmp = in_be32(&gur->rcwsr[3]);
> + for (i = 0; i < cpu_numcores(); i++) {
> + u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf;
> + u32 cplx_pll = core_cplx_PLL[c_pll_sel];
> +
> + sysInfo->freqProcessor[i] = freqCC_PLL[cplx_pll] /
> core_cplx_PLL_div[c_pll_sel];
Line too long, please check globally.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
What about WRITING it first and rationalizing it afterwords? :-)
- Larry Wall in <8...@jpl-devvax.jpl.nasa.gov>
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