On 09/15/2016 09:27 AM, Chin Liang See wrote: > Adding new handoff for SDRAM ctrcfg.extratime1 which is > required for stabil LPDDR2 operation
... stable ... Isn't SoCDK using DDR3 DRAM ? > Signed-off-by: Chin Liang See <cl...@altera.com> > --- > board/altera/arria5-socdk/qts/sdram_config.h | 3 +++ > board/altera/cyclone5-socdk/qts/sdram_config.h | 3 +++ > 2 files changed, 6 insertions(+) > > diff --git a/board/altera/arria5-socdk/qts/sdram_config.h > b/board/altera/arria5-socdk/qts/sdram_config.h > index e9fe60f..8964637 100644 > --- a/board/altera/arria5-socdk/qts/sdram_config.h > +++ b/board/altera/arria5-socdk/qts/sdram_config.h > @@ -49,6 +49,9 @@ > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 > +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 > +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 > +#define > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 > #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 > #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 > #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0 > diff --git a/board/altera/cyclone5-socdk/qts/sdram_config.h > b/board/altera/cyclone5-socdk/qts/sdram_config.h > index 37c1476..1bc6f6f 100644 > --- a/board/altera/cyclone5-socdk/qts/sdram_config.h > +++ b/board/altera/cyclone5-socdk/qts/sdram_config.h > @@ -49,6 +49,9 @@ > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 > +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 > +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 > +#define > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 > #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 > #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 > #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0 > -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
