> -----Original Message-----
> From: Kumar Gala [mailto:ga...@kernel.crashing.org] 
> Sent: Saturday, September 19, 2009 2:42 AM
> To: Hu Mingkai-B21284
> Cc: u-boot@lists.denx.de; Wood Scott-B07421
> Subject: Re: [PATCH v3 1/3] NAND boot: MPC8536DS support
> 
> > +
> > +#include <common.h>
> > +#include <asm/io.h>
> > +
> > +void cpu_init_f(void)
> > +{
> > +   ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
> > +
> > +   /*
> > +    * LCRR - Clock Ratio Register - set up local bus timing
> > +    * when needed
> > +    */
> > +   out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
> > +
> > +#if defined(CONFIG_NAND_BR_PRELIM)  \
> > +   && defined(CONFIG_NAND_OR_PRELIM)
> > +   out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
> > +   out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
> > +   /* for FPGA */
> > +   out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
> > +   out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM); #else #error  
> > +CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined #endif
> > +
> 
> Should we not have br/or1, br/or2, etc?
> 

In order to boot from NAND, it should be connected on br/or0, so we
don't care br/or1, br/or2.
The br/or3 shoud be moved to board specific file nand_boot.c, as dave
pointed, owing to different
connection between the different borads.

Thanks,
Mingkai
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