Hi Chris,
On 22.08.2016 02:38, Chris Packham wrote:
From: Chris Packham <chris.pack...@alliedtelesis.co.nz>
Add pin control settings for the NAND flash interface. This interface
is multiplexed with the device bus interface to the function is "dev"
not "nand" as one might expect.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
Cc: Luka Perkov <luka.per...@sartura.hr>
Cc: Dirk Eibach <eib...@gdsys.de>
---
I don't think this is strictly necessary. A quick scan of boards that
use this family of processor all seem to set their MPP configurations
manually.
Correct. Unfortunately we don't have a pin-ctrl driver for AXP / A38x
in U-Boot yet. Such a driver would be very welcome though. ;)
Another issue is that technically on the Armada-385 there are 4 possible
CE pins. The board I'm looking at happens to use CE#0 (mpp25) but mpp26,
mpp27 and mpp6 are all potentially available. I guess if any boards
actually use them they can add them to their pin specification. At the
very least such boards would need to update the num-cs property anyway.
How is this handled in the kernel? I would very much like to see
these changes in the dts in sync with the kernel as much as
possible. Does the kernel also use "dev" instead of "nand" here?
Thanks,
Stefan
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