On Sun, Aug 14, 2016 at 03:03:15PM +0000, Karl Beldan wrote: > ATM the rx and tx descriptors are handled as cached memory while they > lie in a dedicated RAM of the SoCs, which is an uncached area. > Removing the said dcache ops, while optimizing the logic and clarifying > the code, also gets rid of most of the check_cache_range() incurred > warnings: > CACHE: Misaligned operation at range > > Signed-off-by: Karl Beldan <karl.beldan+...@gmail.com>
Reviewed-by: Tom Rini <tr...@konsulko.com> -- Tom
signature.asc
Description: Digital signature
_______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
