On 07/27/2016 04:26 PM, Paul Burton wrote:
> This patch introduces support for building U-Boot to run on the MIPS
> Boston development board. This is a board built around an FPGA & an
> Intel EG20T Platform Controller Hub, used largely as part of the
> development of new CPUs and their software support. It is essentially
> the successor to the older MIPS Malta board.
>
> Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
[...]
> +++ b/board/imgtec/boston/boston-regs.h
> @@ -0,0 +1,47 @@
> +/*
> + * Copyright (C) 2016 Imagination Technologies
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#ifndef __BOARD_BOSTON_REGS_H__
> +#define __BOARD_BOSTON_REGS_H__
> +
> +#define BOSTON_PLAT_BASE 0x17ffd000
> +#define BOSTON_LCD_BASE 0x17fff000
> +
> +/*
> + * Platform Register Definitions
> + */
> +#define BOSTON_PLAT_CORE_CL 0x04
> +
> +#define BOSTON_PLAT_DDR3STAT 0x14
> +# define BOSTON_PLAT_DDR3STAT_CALIB (1 << 2)
> +
> +#define BOSTON_PLAT_MMCMDIV 0x30
> +# define BOSTON_PLAT_MMCMDIV_CLK0DIV (0xff << 0)
> +# define BOSTON_PLAT_MMCMDIV_INPUT (0xff << 8)
> +# define BOSTON_PLAT_MMCMDIV_MUL (0xff << 16)
> +# define BOSTON_PLAT_MMCMDIV_CLK1DIV (0xff << 24)
> +
> +#define BOSTON_PLAT_DDRCONF0 0x38
> +# define BOSTON_PLAT_DDRCONF0_SIZE (0xf << 0)
> +
> +#ifndef __ASSEMBLY__
> +
> +#include <asm/io.h>
> +
> +#define BUILD_PLAT_ACCESSORS(offset, name) \
> +static inline uint32_t read_boston_##name(void)
> \
> +{ \
> + uint32_t *reg = (void *)CKSEG1ADDR(BOSTON_PLAT_BASE) + (offset);\
> + return __raw_readl(reg); \
> +}
Don't we have enough standard accessors to confuse people ?
Why do you add another custom ones ? Remove this and just use
standard accessors throughout the code.
> +BUILD_PLAT_ACCESSORS(BOSTON_PLAT_CORE_CL, core_cl)
> +BUILD_PLAT_ACCESSORS(BOSTON_PLAT_MMCMDIV, mmcmdiv)
> +BUILD_PLAT_ACCESSORS(BOSTON_PLAT_DDRCONF0, ddrconf0)
> +
> +#endif /* !__ASSEMBLY__ */
> +
> +#endif /* __BOARD_BOSTON_REGS_H__ */
> diff --git a/board/imgtec/boston/checkboard.c
> b/board/imgtec/boston/checkboard.c
> new file mode 100644
> index 0000000..417ac4e
> --- /dev/null
> +++ b/board/imgtec/boston/checkboard.c
> @@ -0,0 +1,29 @@
> +/*
> + * Copyright (C) 2016 Imagination Technologies
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include <common.h>
> +
> +#include <asm/mipsregs.h>
> +
> +#include "boston-lcd.h"
> +#include "boston-regs.h"
>
> +int checkboard(void)
> +{
> + u32 changelist;
> +
> + lowlevel_display("U-boot ");
> +
> + printf("Board: MIPS Boston\n");
> +
> + printf("CPU: 0x%08x", read_c0_prid());
This should be in print_cpuinfo()
> + changelist = read_boston_core_cl();
> + if (changelist > 1)
> + printf(" cl%x", changelist);
> + putc('\n');
> +
> + return 0;
> +}
> diff --git a/board/imgtec/boston/ddr.c b/board/imgtec/boston/ddr.c
> new file mode 100644
> index 0000000..7caed4b
> --- /dev/null
> +++ b/board/imgtec/boston/ddr.c
> @@ -0,0 +1,30 @@
> +/*
> + * Copyright (C) 2016 Imagination Technologies
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include <common.h>
> +
> +#include <asm/addrspace.h>
> +
> +#include "boston-regs.h"
> +
> +phys_size_t initdram(int board_type)
> +{
> + u32 ddrconf0 = read_boston_ddrconf0();
> +
> + return (phys_size_t)(ddrconf0 & BOSTON_PLAT_DDRCONF0_SIZE) << 30;
> +}
> +
> +ulong board_get_usable_ram_top(ulong total_size)
> +{
> + DECLARE_GLOBAL_DATA_PTR;
> +
> + if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) {
> + /* 2GB wrapped around to 0 */
> + return CKSEG0ADDR(256 << 20);
> + }
> +
> + return min_t(unsigned long, gd->ram_top, CKSEG0ADDR(256 << 20));
> +}
> diff --git a/board/imgtec/boston/lowlevel_init.S
> b/board/imgtec/boston/lowlevel_init.S
> new file mode 100644
> index 0000000..8928172
> --- /dev/null
> +++ b/board/imgtec/boston/lowlevel_init.S
> @@ -0,0 +1,56 @@
> +/*
> + * Copyright (C) 2016 Imagination Technologies
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include <config.h>
> +
> +#include <asm/addrspace.h>
> +#include <asm/asm.h>
> +#include <asm/mipsregs.h>
> +#include <asm/regdef.h>
> +
> +#include "boston-regs.h"
> +
> +.data
> +
> +msg_ddr_cal: .ascii "DDR Cal "
> +msg_ddr_ok: .ascii "DDR OK "
> +
> +.text
> +
> +LEAF(lowlevel_init)
> + move s0, ra
> +
> + PTR_LA a0, msg_ddr_cal
> + bal lowlevel_display
Don't you need nop after branch on mips ?
> +
> + PTR_LI t0, CKSEG1ADDR(BOSTON_PLAT_BASE)
> +1: lw t1, BOSTON_PLAT_DDR3STAT(t0)
> + andi t1, t1, BOSTON_PLAT_DDR3STAT_CALIB
> + beqz t1, 1b
> +
> + PTR_LA a0, msg_ddr_ok
> + bal lowlevel_display
> +
> + move v0, zero
> + jr s0
> + END(lowlevel_init)
> +
> +LEAF(lowlevel_display)
> + .set push
> + .set noat
> + PTR_LI AT, CKSEG1ADDR(BOSTON_LCD_BASE)
> +#ifdef CONFIG_64BIT
> + ld k1, 0(a0)
> + sd k1, 0(AT)
> +#else
> + lw k1, 0(a0)
> + sw k1, 0(AT)
> + lw k1, 4(a0)
> + sw k1, 4(AT)
> +#endif
> + .set pop
> +1: jr ra
> + END(lowlevel_display)
> diff --git a/configs/boston_defconfig b/configs/boston_defconfig
> new file mode 100644
> index 0000000..381203a
> --- /dev/null
> +++ b/configs/boston_defconfig
> @@ -0,0 +1,41 @@
> +CONFIG_MIPS=y
> +CONFIG_TARGET_BOSTON=y
> +CONFIG_SYS_LITTLE_ENDIAN=y
> +CONFIG_CPU_MIPS64_R6=y
> +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
> +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
> +CONFIG_MIPS_BOOT_FDT=y
> +CONFIG_DEFAULT_DEVICE_TREE="img,boston"
> +CONFIG_FIT=y
> +CONFIG_FIT_VERBOSE=y
> +CONFIG_FIT_BEST_MATCH=y
> +CONFIG_OF_STDOUT_VIA_ALIAS=y
> +CONFIG_SYS_NO_FLASH=y
> +CONFIG_HUSH_PARSER=y
> +CONFIG_SYS_PROMPT="boston # "
> +# CONFIG_CMD_ELF is not set
> +# CONFIG_CMD_IMLS is not set
> +CONFIG_CMD_GREPENV=y
> +CONFIG_CMD_MEMTEST=y
> +# CONFIG_CMD_LOADB is not set
> +# CONFIG_CMD_LOADS is not set
> +# CONFIG_CMD_FPGA is not set
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_SNTP=y
> +CONFIG_CMD_DNS=y
> +CONFIG_CMD_LINK_LOCAL=y
> +CONFIG_CMD_TIME=y
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_CMD_FAT=y
> +CONFIG_CMD_FS_GENERIC=y
> +CONFIG_OF_EMBED=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_CLK=y
> +CONFIG_DM_ETH=y
> +CONFIG_PCH_GBE=y
> +CONFIG_DM_PCI=y
> +CONFIG_PCI_XILINX=y
> +CONFIG_SYS_NS16550=y
> +CONFIG_LZ4=y
> diff --git a/include/configs/boston.h b/include/configs/boston.h
> new file mode 100644
> index 0000000..e25c8d5
> --- /dev/null
> +++ b/include/configs/boston.h
> @@ -0,0 +1,68 @@
> +/*
> + * Copyright (C) 2016 Imagination Technologies
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#ifndef __CONFIGS_BOSTON_H__
> +#define __CONFIGS_BOSTON_H__
> +
> +/*
> + * General board configuration
> + */
> +#define CONFIG_DISPLAY_BOARDINFO
> +
> +/*
> + * CPU
> + */
> +#define CONFIG_SYS_MIPS_TIMER_FREQ 30000000
> +
> +/*
> + * PCI
> + */
> +#define CONFIG_PCI
> +#define CONFIG_PCI_PNP
> +#define CONFIG_CMD_PCI
> +
> +/*
> + * Environment
> + */
> +#define CONFIG_ENV_IS_NOWHERE
> +#define CONFIG_ENV_SIZE 1024
> +
> +/*
> + * Memory map
> + */
> +#ifdef CONFIG_64BIT
> +# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
> +#else
> +# define CONFIG_SYS_SDRAM_BASE 0x80000000
> +#endif
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
> +
> +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
> +
> +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100000)
> +
> +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0)
> +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE +
> 0x10000000)
> +
> +#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
> +
> +/*
> + * Console
> + */
> +#define CONFIG_SYS_MAXARGS 16
> +#define CONFIG_SYS_CBSIZE 256
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
> + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_LONGHELP
> +#define CONFIG_BAUDRATE 115200
> +
> +/*
> + * Flash
> + */
> +#define CONFIG_SYS_MAX_FLASH_BANKS 1
> +
> +#endif /* __CONFIGS_BOSTON_H__ */
>
--
Best regards,
Marek Vasut
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