On 27/07/16 12:37, Daniel Schwierzeck wrote:
+#define EXT(field) ((mmcmdiv & field) >> (ffs(field) - 1))
+
+ in_rate = EXT(BOSTON_PLAT_MMCMDIV_INPUT);
+ mul = EXT(BOSTON_PLAT_MMCMDIV_MUL);
+ clk0_div = EXT(BOSTON_PLAT_MMCMDIV_CLK0DIV);
+
+#undef EXT
+
+ clk0_rate = (in_rate * mul * 1000000) / clk0_div;
+
+ err = fdt_setprop_inplace_u32(fdt, clk_off, "clock-frequency",
+ clk0_rate);
+ if (err)
+ printf("%s: failed to set clock-frequency\n", __func__);
+}
Couldn't you create a simple clk driver with this code and use that as
clock source? Using the fixed-clk driver and patching the DT properties
seems a little bit strange.
Hi Daniel,
What the system provides is just a fixed rate clock, whose rate is
determined by the bitfile programmed on the FPGA. I guess I could model
it with its own clock driver.
+LEAF(lowlevel_display)
+ .set push
+ .set noat
+ PTR_LI $1, CKSEG1ADDR(BOSTON_LCD_BASE)
isn't it better to use the symbolic name AT from asm/regdef.h instead of
$1?
OK, will do.
Thanks,
Paul
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