Hi Stefan, On Thu, Jul 7, 2016 at 11:52 PM, Stefan Roese <s...@denx.de> wrote: > Hi! > > I do have BayTrail / FSP related question. I'm currently trying > to use a DFI QSeven SoM which has one x4 PCIe slot instead > of the usual 4 x1 slots. So all 4 PCIe lanes are used by the > first PCIe controller. With the current U-Boot, all 4 PCIe > controllers are enabled by the FSP : > > 00:1c.0 PCI bridge: Intel Corporation Atom Processor E3800 Series PCI Express > Root Port 1 (rev 11) > 00:1c.1 PCI bridge: Intel Corporation Atom Processor E3800 Series PCI Express > Root Port 2 (rev 11) > 00:1c.2 PCI bridge: Intel Corporation Atom Processor E3800 Series PCI Express > Root Port 3 (rev 11) > 00:1c.3 PCI bridge: Intel Corporation Atom Processor E3800 Series PCI Express > Root Port 4 (rev 11) > > In this configuration, the x4 PCIe card that is installed in the > PCIe slot is not detected. The system always generated hotplug > events for all for ports, but the link is not established. > > The original DFI BIOS only enables the first PCIe controller. The > controllers 1...3 are not visible via lspci. Here the 4x link > is established and the 4x PCIe card is detected correctly. > > My question now is, how can I enable this 4x link on the first > PCIe controller via U-Boot / FSP? I have found no option on how > to configure the PCIe controllers in the FSP dts properties. > So that only the first controller is enabled and visible via > lspci etc. The BayTrail datasheet mentions this to configure the > PCIe setup in chapter "23.2.1 Root Port Configurations": > > " > Root port configurations are set by SoftStraps stored in SPI flash, > and the default option is “(4) x1”. Links for each root port will > train automatically to the maximum possible for each port. > " >
Correct. It's determined by the soft strap value in the SPI flash, to be specific, in the descriptor.bin. > Where is this SoftStraps in the SPI flash located? I've found this > page mentioning that its a offset 0x100: > > https://embedded.communities.intel.com/thread/8539 > > But I fail to find any documentation for all those Soft-Strap > Registers / Values in the SPI flash. Does anyone have some further > infos / documentation on this? How to enable 4x PCIe lanes > for one PCIe controller on BayTrail / Atom? > Please try this: If you have the original DFI BIOS, extract the descriptor.bin using U-Boot's ifdtool (ifdtool -x dfi_bios), and use this descriptor.bin to generate u-boot.rom. Or if you don't have the original DFI BIOS, dump it using Dediprog SF100, and do the same. Regards, Bin _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
