As CONFIG_ARMV8_SWITCH_TO_EL1 is not used now, this patch is to remove
CONFIG_ARMV8_SWITCH_TO_EL1 and the corresponding functions.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 13 --------
arch/arm/cpu/armv8/start.S | 5 +--
arch/arm/cpu/armv8/transition.S | 6 ----
arch/arm/include/asm/macro.h | 47 ----------------------------
arch/arm/include/asm/system.h | 1 -
arch/arm/lib/bootm.c | 3 --
arch/arm/mach-exynos/soc.c | 1 -
include/configs/vexpress_aemv8a.h | 1 -
include/configs/xilinx_zynqmp.h | 2 --
9 files changed, 1 insertion(+), 78 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 5af6b73..d3a0117 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -325,19 +325,12 @@ ENTRY(secondary_boot_func)
#endif
bl secondary_switch_to_el2
-#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
- bl secondary_switch_to_el1
-#endif
slave_cpu:
wfe
ldr x0, [x11]
cbz x0, slave_cpu
-#ifndef CONFIG_ARMV8_SWITCH_TO_EL1
mrs x1, sctlr_el2
-#else
- mrs x1, sctlr_el1
-#endif
tbz x1, #25, cpu_is_le
rev x0, x0 /* BE to LE conversion */
cpu_is_le:
@@ -350,12 +343,6 @@ ENTRY(secondary_switch_to_el2)
1: armv8_switch_to_el2_m x0
ENDPROC(secondary_switch_to_el2)
-ENTRY(secondary_switch_to_el1)
- switch_el x0, 0f, 1f, 0f
-0: ret
-1: armv8_switch_to_el1_m x0, x1
-ENDPROC(secondary_switch_to_el1)
-
/* Ensure that the literals used by the secondary boot code are
* assembled within it (this is required so that we can protect
* this area with a single memreserve region
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 670e323..ab434a6 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -242,12 +242,9 @@ WEAK(lowlevel_init)
#endif
/*
- * All slaves will enter EL2 and optionally EL1.
+ * All slaves will enter EL2.
*/
bl armv8_switch_to_el2
-#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
- bl armv8_switch_to_el1
-#endif
#endif /* CONFIG_ARMV8_MULTIENTRY */
diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S
index 253a39b..209d5c8 100644
--- a/arch/arm/cpu/armv8/transition.S
+++ b/arch/arm/cpu/armv8/transition.S
@@ -15,9 +15,3 @@ ENTRY(armv8_switch_to_el2)
0: ret
1: armv8_switch_to_el2_m x0
ENDPROC(armv8_switch_to_el2)
-
-ENTRY(armv8_switch_to_el1)
- switch_el x0, 0f, 1f, 0f
-0: ret
-1: armv8_switch_to_el1_m x0, x1
-ENDPROC(armv8_switch_to_el1)
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index 9bb0efa..c1b3452 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -167,53 +167,6 @@ lr .req x30
eret
.endm
-.macro armv8_switch_to_el1_m, xreg1, xreg2
- /* Initialize Generic Timers */
- mrs \xreg1, cnthctl_el2
- orr \xreg1, \xreg1, #0x3 /* Enable EL1 access to timers */
- msr cnthctl_el2, \xreg1
- msr cntvoff_el2, xzr
-
- /* Initilize MPID/MPIDR registers */
- mrs \xreg1, midr_el1
- mrs \xreg2, mpidr_el1
- msr vpidr_el2, \xreg1
- msr vmpidr_el2, \xreg2
-
- /* Disable coprocessor traps */
- mov \xreg1, #0x33ff
- msr cptr_el2, \xreg1 /* Disable coprocessor traps to EL2 */
- msr hstr_el2, xzr /* Disable coprocessor traps to EL2 */
- mov \xreg1, #3 << 20
- msr cpacr_el1, \xreg1 /* Enable FP/SIMD at EL1 */
-
- /* Initialize HCR_EL2 */
- mov \xreg1, #(1 << 31) /* 64bit EL1 */
- orr \xreg1, \xreg1, #(1 << 29) /* Disable HVC */
- msr hcr_el2, \xreg1
-
- /* SCTLR_EL1 initialization
- *
- * setting RES1 bits (29,28,23,22,20,11) to 1
- * and RES0 bits (31,30,27,21,17,13,10,6) +
- * UCI,EE,EOE,WXN,nTWE,nTWI,UCT,DZE,I,UMA,SED,ITD,
- * CP15BEN,SA0,SA,C,A,M to 0
- */
- mov \xreg1, #0x0800
- movk \xreg1, #0x30d0, lsl #16
- msr sctlr_el1, \xreg1
-
- /* Return to the EL1_SP1 mode from EL2 */
- mov \xreg1, sp
- msr sp_el1, \xreg1 /* Migrate SP */
- mrs \xreg1, vbar_el2
- msr vbar_el1, \xreg1 /* Migrate VBAR */
- mov \xreg1, #0x3c5
- msr spsr_el2, \xreg1 /* EL1_SP1 | D | A | I | F */
- msr elr_el2, lr
- eret
-.endm
-
#if defined(CONFIG_GICV3)
.macro gic_wait_for_interrupt_m xreg1
0 : wfi
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 2bdc0be..3a22661 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -101,7 +101,6 @@ int __asm_flush_l3_cache(void);
void __asm_switch_ttbr(u64 new_ttbr);
void armv8_switch_to_el2(void);
-void armv8_switch_to_el1(void);
void gic_init(void);
void gic_send_sgi(unsigned long sgino);
void wait_for_wakeup(void);
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 0838d89..e3c9832 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -194,9 +194,6 @@ static void do_nonsec_virt_switch(void)
smp_kick_all_cpus();
dcache_disable(); /* flush cache before swtiching to EL2 */
armv8_switch_to_el2();
-#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
- armv8_switch_to_el1();
-#endif
}
#endif
diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c
index f9c7468..c27a389 100644
--- a/arch/arm/mach-exynos/soc.c
+++ b/arch/arm/mach-exynos/soc.c
@@ -28,6 +28,5 @@ void enable_caches(void)
void lowlevel_init(void)
{
armv8_switch_to_el2();
- armv8_switch_to_el1();
}
#endif
diff --git a/include/configs/vexpress_aemv8a.h
b/include/configs/vexpress_aemv8a.h
index 46cf83b..05bae44 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -12,7 +12,6 @@
#ifndef CONFIG_SEMIHOSTING
#error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
#endif
-#define CONFIG_ARMV8_SWITCH_TO_EL1
#endif
#define CONFIG_REMAKE_ELF
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index e776e32..c858491 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -13,8 +13,6 @@
#define CONFIG_REMAKE_ELF
-/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */
-
#define CONFIG_SYS_NO_FLASH
/* Generic Interrupt Controller Definitions */
--
2.1.0.27.g96db324
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