On 10/06/2016 17:07, Diego Dorta wrote:
> Pico-imx6ul has a KSZ8081 Ethernet PHY.
>
> Add support for it.
>
> Signed-off-by: Diego Dorta <diego.do...@nxp.com>
> ---
> board/technexion/pico-imx6ul/pico-imx6ul.c | 84
> ++++++++++++++++++++++++++++++
> include/configs/pico-imx6ul.h | 10 ++++
> 2 files changed, 94 insertions(+)
>
> diff --git a/board/technexion/pico-imx6ul/pico-imx6ul.c
> b/board/technexion/pico-imx6ul/pico-imx6ul.c
> index c038d43..fc746ec 100644
> --- a/board/technexion/pico-imx6ul/pico-imx6ul.c
> +++ b/board/technexion/pico-imx6ul/pico-imx6ul.c
> @@ -16,6 +16,8 @@
> #include <asm/imx-common/iomux-v3.h>
> #include <asm/io.h>
> #include <common.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> #include <fsl_esdhc.h>
> #include <linux/sizes.h>
> #include <usb.h>
> @@ -34,6 +36,87 @@ DECLARE_GLOBAL_DATA_PTR;
> PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
> PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
>
> +#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
> + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
> +
> +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
> + PAD_CTL_SPEED_HIGH | \
> + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
> +
> +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
> +
> +#define RMII_PHY_RESET IMX_GPIO_NR(1, 28)
> +
> +static iomux_v3_cfg_t const fec_pads[] = {
> + MX6_PAD_ENET1_TX_EN__ENET2_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL),
> + MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
> + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 |
> MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
> + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static void setup_iomux_fec(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> + setup_iomux_fec();
> +
> + gpio_direction_output(RMII_PHY_RESET, 0);
> + /*
> + * According to KSZ8081MNX-RNB manual:
> + * For warm reset, the reset (RST#) pin should be asserted low for a
> + * minimum of 500μs. The strap-in pin values are read and updated
> + * at the de-assertion of reset.
> + */
> + udelay(500);
> +
> + gpio_direction_output(RMII_PHY_RESET, 1);
> + /*
> + * According to KSZ8081MNX-RNB manual:
> + * After the de-assertion of reset, wait a minimum of 100μs before
> + * starting programming on the MIIM (MDC/MDIO) interface.
> + */
> + udelay(100);
> +
> + return fecmxc_initialize(bis);
> +}
> +
> +static int setup_fec(void)
> +{
> + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
> + int ret;
> +
> + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
> + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
> +
> + ret = enable_fec_anatop_clock(1, ENET_50MHZ);
> + if (ret)
> + return ret;
> +
> + enable_enet_clk(1);
> +
> + return 0;
> +}
> +
> +int board_phy_config(struct phy_device *phydev)
> +{
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
> +
> + if (phydev->drv->config)
> + phydev->drv->config(phydev);
> +
> + return 0;
> +}
> +
> int dram_init(void)
> {
> gd->ram_size = imx_ddr_size();
> @@ -106,6 +189,7 @@ int board_init(void)
> /* Address of boot parameters */
> gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
>
> + setup_fec();
> setup_usb();
>
> return 0;
> diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
> index d848ead..73e37e1 100644
> --- a/include/configs/pico-imx6ul.h
> +++ b/include/configs/pico-imx6ul.h
> @@ -17,6 +17,16 @@
> #define CONFIG_DISPLAY_CPUINFO
> #define CONFIG_DISPLAY_BOARDINFO
>
> +/* Network support */
> +
> +#define CONFIG_FEC_MXC
> +#define CONFIG_MII
> +#define IMX_FEC_BASE ENET2_BASE_ADDR
> +#define CONFIG_FEC_MXC_PHYADDR 0x1
> +#define CONFIG_FEC_XCV_TYPE RMII
> +#define CONFIG_PHYLIB
> +#define CONFIG_PHY_MICREL
> +
> /* Size of malloc() pool */
> #define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
>
>
Reviewed-by: Stefano Babic <sba...@denx.de>
Best regards,
Stefano Babic
--
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