The end address of the cache flush must be cache-line-aligned since
otherwise (at least on ARM926-EJS) the request is ignored. When the cache
is enabled this means that packets are not sent.
Signed-off-by: Simon Glass <s...@chromium.org>
Reviewed-by: Heiko Schocher <h...@denx.de>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>
---
Changes in v2: None
drivers/net/macb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index f0af40c..ecdfc1b 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -280,7 +280,7 @@ static int _macb_send(struct macb_device *macb, const char
*name, void *packet,
barrier();
macb_flush_ring_desc(macb, TX);
/* Do we need check paddr and length is dcache line aligned? */
- flush_dcache_range(paddr, paddr + length);
+ flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN));
macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
/*
--
2.8.0.rc3.226.g39d4020
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