> -----Original Message-----
> From: Yunhui Cui <b56...@freescale.com>
> Date: Sun, Apr 10, 2016 at 9:37 PM
> Subject: [U-Boot] [PATCH v2] armv8/ls2080a: configure PMU's PCTBENR to
> enable WDT
> To: york....@nxp.com
> Cc: yunhui....@nxp.com, u-boot@lists.denx.de
>
>
> From: Yunhui Cui <yunhui....@nxp.com>
>
> The SP805-WDT module on LS2080A and LS2085A, requires configuration
> of PMU's PCTBENR register to enable watchdog counter decrement and
> reset signal generation. In order not to affect the sp805wdt driver
> frame, we enable the watchdog clk in advance.
>
> Signed-off-by: Yunhui Cui <yunhui....@nxp.com>
> ---
> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 17 +++++++++++++++++
> arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 ++++
> arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 +
> board/freescale/ls2080aqds/ls2080aqds.c | 2 ++
> board/freescale/ls2080ardb/ls2080ardb.c | 2 ++
> 5 files changed, 26 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> index a76447e..e6f3566 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> @@ -17,6 +17,23 @@
> #endif
>
> DECLARE_GLOBAL_DATA_PTR;
> +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
Yunhui, I thought that York recently sent patches to get rid of
CONFIG_LS2085A.
See the patch:
[PATCH v3] armv8: LS2080A: Consolidate LS2080A and LS2085A
> +/*
> + * There are eight SP805 watchdog units on ls2080a/ls2085a,So
> + * Set PMU-Physical Core Time Base Enable Register (PCTBENR)
> + * low eight bits to enable clocks to eight Cortext-A57 cores
> + * timebase, which allows the WDT counter to decrement and raise
> + * a reset request (if configured in the WDTCONTROL register).
> + */
I think this is getting too specific and adds unnecessary details.
What if we have A72 cores? ...as we will soon. What about other
SoCs? Just say:
/*
* In certain Layerscape SoCs, the clock for each core's watchdog
* has an enable bit in the PMU Physical Core Time Base Enable Register
* PCTBENR), which allows the watchdog to operate.
*/
Thanks,
Stuart
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