For LS1021A Secure Boot, SPARE2 register is used and modified by the
IBR. To avoid the conflict, SPARE4 is used instead of SPARE2 to store
the entry point of kernel. This patch is to get the entry point of
kernel from SPARE4 instead of SPARE2.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
---
board/freescale/common/arm_sleep.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/common/arm_sleep.c
b/board/freescale/common/arm_sleep.c
index 71ed15e..6d967f0 100644
--- a/board/freescale/common/arm_sleep.c
+++ b/board/freescale/common/arm_sleep.c
@@ -88,7 +88,7 @@ int fsl_dp_resume(void)
dp_resume_prepare();
/* Get the entry address and jump to kernel */
- start_addr = in_le32(&scfg->sparecr[1]);
+ start_addr = in_le32(&scfg->sparecr[3]);
debug("Entry address is 0x%08x\n", start_addr);
kernel_resume = (void (*)(void))start_addr;
secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0);
--
2.1.0.27.g96db324
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
