Hi Heiko,
One minor critique, I had problems parsing the comment:
Heiko Schocher wrote:
> MPC8379E RM says (10-34):
> Once LCRR[CLKDIV] is written, the register should be read, and then
> an isync should be executed.
> So update this in code.
> Also define a LCRR mask for processors, which uses not all bits
^^^^^^^^^^^^^^^^^^^^^^^
Suggested change:
Also define a LCRR mask for processors to prevent setting any reserved
bits in the LCRR register (as, for example, mpc832x did).
> in the LCRR register (as for example mpc832x did).
>
> Signed-off-by: Heiko Schocher <h...@denx.de>
Thanks,
gvb
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