Hi Bin,
On 11 March 2016 at 01:34, Bin Meng <bmeng...@gmail.com> wrote:
> Hi Simon,
>
> On Mon, Mar 7, 2016 at 10:28 AM, Simon Glass <s...@chromium.org> wrote:
>> Provide a way to determine the HSIO (high-speed I/O) version supported by
>> the Intel Management Engine (ME) implementation on the platform.
>>
>> Signed-off-by: Simon Glass <s...@chromium.org>
>> ---
>>
>> arch/x86/cpu/broadwell/Makefile | 1 +
>> arch/x86/cpu/broadwell/me.c | 57
>> +++++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 58 insertions(+)
>> create mode 100644 arch/x86/cpu/broadwell/me.c
>>
>> diff --git a/arch/x86/cpu/broadwell/Makefile
>> b/arch/x86/cpu/broadwell/Makefile
>> index 012798f..7edb6f6 100644
>> --- a/arch/x86/cpu/broadwell/Makefile
>> +++ b/arch/x86/cpu/broadwell/Makefile
>> @@ -7,6 +7,7 @@
>> obj-y += cpu.o
>> obj-y += iobp.o
>> obj-y += lpc.o
>> +obj-y += me.o
>> obj-y += northbridge.o
>> obj-y += pch.o
>> obj-y += pinctrl_broadwell.o
>> diff --git a/arch/x86/cpu/broadwell/me.c b/arch/x86/cpu/broadwell/me.c
>> new file mode 100644
>> index 0000000..e03b87c
>> --- /dev/null
>> +++ b/arch/x86/cpu/broadwell/me.c
>> @@ -0,0 +1,57 @@
>> +/*
>> + * Copyright (c) 2016 Google, Inc
>> + *
>> + * SPDX-License-Identifier: GPL-2.0
>
> nits: GPL-2.0+?
>
>> + *
>> + * Based on code from coreboot src/soc/intel/broadwell/me_status.c
>> + */
>> +
>> +#include <common.h>
>> +#include <errno.h>
>> +#include <asm/arch/me.h>
>> +
>> +static inline void me_read_dword_ptr(struct udevice *dev, void *ptr, int
>> offset)
>> +{
>> + u32 dword;
>> +
>> + dm_pci_read_config32(dev, offset, &dword);
>> + memcpy(ptr, &dword, sizeof(dword));
>
> Why not just use dm_pci_read_config32()?
See the previous patch where this is used. We are writing into a
bitfield struct. Somewhat horrible.
>
>> +}
>> +
>> +int intel_me_hsio_version(struct udevice *dev, uint16_t *versionp,
>> + uint16_t *checksump)
>> +{
>> + int count;
>> + u32 hsiover;
>> + struct me_hfs hfs;
>> +
>> + /* Query for HSIO version, overloads H_GS and HFS */
>> + dm_pci_write_config32(dev, PCI_ME_H_GS,
>> + ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER);
>> +
>> + /* Must wait for ME acknowledgement */
>> + for (count = ME_RETRY; count > 0; --count) {
>> + me_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
>> + if (hfs.bios_msg_ack)
>> + break;
>> + udelay(ME_DELAY);
>> + }
>> + if (!count) {
>> + debug("ERROR: ME failed to respond\n");
>> + return -ETIMEDOUT;
>> + }
>> +
>> + /* HSIO version should be in HFS_5 */
>> + dm_pci_read_config32(dev, PCI_ME_HFS5, &hsiover);
>> + *versionp = hsiover >> 16;
>> + *checksump = hsiover & 0xffff;
>> +
>> + debug("ME: HSIO Version : %d (CRC 0x%04x)\n",
>> + *versionp, *checksump);
>> +
>> + /* Reset registers to normal behavior */
>> + dm_pci_write_config32(dev, PCI_ME_H_GS,
>> + ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER);
>> +
>> + return 0;
>> +}
>> --
>
> Regards,
> Bin
Regards,
Simon
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