Given that DRA7/OMAP5 SoCs can support more than 2GB of memory,
enable interleaving for this higher memory to increase performance.
Signed-off-by: Lokesh Vutla <lokeshvu...@ti.com>
---
arch/arm/cpu/armv7/omap-common/emif-common.c | 2 ++
arch/arm/include/asm/emif.h | 3 +++
2 files changed, 5 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c
b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 3673884..697d6e0 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -1329,6 +1329,8 @@ void dmm_init(u32 base)
&hw_lisa_map_regs->dmm_lisa_map_1);
writel(lisa_map_regs->dmm_lisa_map_0,
&hw_lisa_map_regs->dmm_lisa_map_0);
+
+ setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK);
}
/*
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index b03cf5a..3183130 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -545,6 +545,9 @@
/* Memory Adapter */
#define MA_BASE 0x482AF040
+#define MA_PRIORITY 0x482A2000
+#define MA_HIMEM_INTERLEAVE_UN_SHIFT 8
+#define MA_HIMEM_INTERLEAVE_UN_MASK (1 << 8)
/* DMM_LISA_MAP */
#define EMIF_SYS_ADDR_SHIFT 24
--
2.1.4
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