The eSDHC could select to use platform clock or peripheral clock to
generate SD clock. The default selection is platform clock. So, fix
the clock frequency value that's calculated for eSDHC.
Signed-off-by: Yangbo Lu <yangbo...@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 6f6a588..453a93d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -106,9 +106,13 @@ void get_sys_info(struct sys_info *sys_info)
#define HWA_CGA_M2_CLK_SEL 0x00000007
#define HWA_CGA_M2_CLK_SHIFT 0
#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
rcw_tmp = in_be32(&gur->rcwsr[15]);
rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
+#else
+ sys_info->freq_sdhc = sys_info->freq_systembus;
+#endif
#endif
#if defined(CONFIG_FSL_IFC)
--
2.1.0.27.g96db324
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