On 01/13/2016 07:08 PM, Daniel Schwierzeck wrote:
> Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra Mandal:
>> PIC32 clock module consists of multiple oscillators, PLLs,
>> mutiplexers
>> and dividers capable of supplying clock to various controllers
>> on or off-chip.
>>
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>> Reviewed-by: Simon Glass <s...@chromium.org>
> Reviewed-by: Daniel Schwierzeck <daniel.schwierz...@gmail.com>
>
> nits below
>
>> ---
>>
>> Changes in v3:
>> - rename clk-pic32.c to clk_pic32.c
>> - update clock binding documentation
>> - replace pic32_ioremap() with ioremap()
>> - separate MPLL initialization constants
>>
>> Changes in v2:
>> - add mpll get clock rate
>>
>> .../clock/microchip,pic32-clock.txt | 33 ++
>> drivers/clk/Makefile | 1 +
>> drivers/clk/clk_pic32.c | 433
>> +++++++++++++++++++++
>> include/dt-bindings/clock/microchip,clock.h | 29 ++
>> 4 files changed, 496 insertions(+)
>> create mode 100644 doc/device-tree-bindings/clock/microchip,pic32
>> -clock.txt
>> create mode 100644 drivers/clk/clk_pic32.c
>> create mode 100644 include/dt-bindings/clock/microchip,clock.h
>>
>> diff --git a/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
>> b/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
>> new file mode 100644
>> index 0000000..02e5ce4
>> --- /dev/null
>> +++ b/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
>> @@ -0,0 +1,33 @@
>> +* Microchip PIC32 Clock and Oscillator
>> +
>> +Microchip PIC32 clock tree consists of few oscillators, PLLs,
>> +multiplexers and few divider modules capable of supplying clocks
>> +to various controllers within SoC and also to off-chip.
>> +
>> +PIC32 clock controller output is defined by indices as defined
>> +in [0]
>> +
>> +[0] include/dt-bindings/clock/microchip,clock.h
>> +
>> +Required Properties:
>> +- compatible: should be "microchip,pic32mzda_clk"
>> +- reg: physical base address of the controller and length of memory
>> mapped
>> + region.
>> +- #clock-cells: should be 1.
>> +
>> +Example: Clock controller node:
>> +
>> + clock: clk@1f801200 {
>> + compatible = "microchip,pic32mzda_clk";
>> + reg = <0x1f801200 0x1000>;
>> + };
>> +
>> +Example: UART controller node that consumes the clock generated by
>> the clock
>> +controller:
>> +
>> + uart1: serial@1f822000 {
>> + compatible = "microchip,pic32mzda-uart";
>> + reg = <0xbf822000 0x50>;
>> + interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&clock PB2CLK>;
>> + };
>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>> index 4a6a4a8..adda769 100644
>> --- a/drivers/clk/Makefile
>> +++ b/drivers/clk/Makefile
>> @@ -9,3 +9,4 @@ obj-$(CONFIG_CLK) += clk-uclass.o
>> obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
>> obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
>> obj-$(CONFIG_SANDBOX) += clk_sandbox.o
>> +obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
>> diff --git a/drivers/clk/clk_pic32.c b/drivers/clk/clk_pic32.c
>> new file mode 100644
>> index 0000000..bb0a1cf
>> --- /dev/null
>> +++ b/drivers/clk/clk_pic32.c
>> @@ -0,0 +1,433 @@
>> +/*
>> + * Copyright (C) 2015 Purna Chandra Mandal <
>> purna.man...@microchip.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + *
>> + */
>> +
>> [...]
>> +
>> +static ulong pic32_set_periph_rate(struct udevice *dev, int periph,
>> ulong rate)
>> +{
>> + struct pic32_clk_priv *priv = dev_get_priv(dev);
>> + ulong pll_hz;
>> +
>> + switch (periph) {
>> + case REF1CLK ... REF5CLK:
>> + pll_hz = pic32_get_pll_rate(priv);
>> + pic32_set_refclk(priv, periph, pll_hz, rate,
>> ROCLK_SRC_SPLL);
>> + break;
>> + default:
>> + break;
>> + }
>> +
>> + return rate;
>> +}
>> +
>> +static struct clk_ops pic32_pic32_clk_ops = {
>> + .get_rate = pic32_clk_get_rate,
>> + .set_periph_rate = pic32_set_periph_rate,
>> + .get_periph_rate = pic32_get_periph_rate,
>> +};
>> +
>> +static int pic32_clk_probe(struct udevice *dev)
>> +{
>> + struct pic32_clk_priv *priv = dev_get_priv(dev);
>> + fdt_addr_t addr;
>> + fdt_size_t size;
>> +
>> + addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset,
>> "reg", &size);
>> + if (addr == FDT_ADDR_T_NONE)
>> + return -EINVAL;
>> +
>> + priv->iobase = ioremap(addr, size);
>> + if (!priv->iobase)
>> + return -EINVAL;
> you can drop this check. ioremap() always returns a mapped address
ack. Will drop.
>> +
>> + priv->syscfg_base = pic32_get_syscfg_base();
>> +
>> + /* initialize clocks */
>> + pic32_clk_init(dev);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct udevice_id pic32_clk_ids[] = {
>> + { .compatible = "microchip,pic32mzda_clk"},
>> + {}
>> +};
>> +
>> +U_BOOT_DRIVER(pic32_clk) = {
>> + .name = "pic32_clk",
>> + .id = UCLASS_CLK,
>> + .of_match = pic32_clk_ids,
>> + .flags = DM_FLAG_PRE_RELOC,
>> + .ops = &pic32_pic32_clk_ops,
>> + .probe = pic32_clk_probe,
>> + .priv_auto_alloc_size = sizeof(struct pic32_clk_priv),
>> +};
>> diff --git a/include/dt-bindings/clock/microchip,clock.h b/include/dt
>> -bindings/clock/microchip,clock.h
>> new file mode 100644
>> index 0000000..93c222d
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/microchip,clock.h
>> @@ -0,0 +1,29 @@
>> +/*
>> + * (c) 2015 Purna Chandra Mandal <purna.man...@microchip.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + *
>> + */
>> +
>> +#ifndef __CLK_MICROCHIP_PIC32
>> +#define __CLK_MICROCHIP_PIC32
>> +
>> +/* clock output indices */
>> +#define BASECLK 0
>> +#define PLLCLK 1
>> +#define MPLL 2
>> +#define SYSCLK 3
>> +#define PB1CLK 4
>> +#define PB2CLK 5
>> +#define PB3CLK 6
>> +#define PB4CLK 7
>> +#define PB5CLK 8
>> +#define PB6CLK 9
>> +#define PB7CLK 10
>> +#define REF1CLK 11
>> +#define REF2CLK 12
>> +#define REF3CLK 13
>> +#define REF4CLK 14
>> +#define REF5CLK 15
>> +
>> +#endif /* __CLK_MICROCHIP_PIC32 */
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