On Monday, December 21, 2015 at 03:37:28 PM, Chin Liang See wrote:
> On Mon, 2015-12-21 at 15:19 +0100, Marek Vasut wrote:
> > On Monday, December 21, 2015 at 01:25:03 PM, Chin Liang See wrote:
> > > On Mon, 2015-12-21 at 11:09 +0100, Marek Vasut wrote:
> > > > On Monday, December 21, 2015 at 10:50:50 AM, Chin Liang See
> > >
> > > > wrote:
> > > [..]
> > >
> > > > > Hmmm, here is the function for L2 cache within my development
> > > > > branch.
> > > > > Some of the latency tuning helps based on the benchmark result.
> > > > > Probably you can give it a try, Marek?
> > > > >
> > > > > void v7_outer_cache_enable(void)
> > > > > {
> > > > >
> > > > > /* disable the L2 cache */
> > > > > writel(0, &pl310_regs_base->pl310_ctrl);
> > > > >
> > > > > /* enable BRESP, instruction and data prefetch, full
> > > > >
> > > > > line of
> > > > >
> > > > > zeroes */
> > > > >
> > > > > setbits_le32(&pl310_regs_base->pl310_aux_ctrl,
> > > > >
> > > > > PL310_AUX_CTRL_FULL_LINE_ZERO_MASK |
> > > > > PL310_AUX_CTRL_DATA_PREFETCH_MASK |
> > > > > PL310_AUX_CTRL_INST_PREFETCH_MASK |
> > > > > PL310_AUX_CTRL_EARLY_BRESP_MASK);
> > > > >
> > > > > /* setup tag ram latency */
> > > > > writel(0, &pl310_regs_base->pl310_tag_latency_ctrl);
> > > >
> > > > Are you _sure_ this is a good idea to set the latency to 0x0 ?
> > >
> > > Actually it still have 1 cycle of latency, just no additional
> >
> > And that's OK on socfpga ? I would've expected some latency here.
>
> Yup, Linux is using the same value too
> https://github.com/altera-opensource/linux-socfpga/blob/master/arch/arm
> /boot/dts/socfpga.dtsi
I find the value a bit odd, since other CortexA9 machines which I used always
configured that to something higher than 0 . Can anyone comment on that ?
Best regards,
Marek Vasut
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
