On Sun, 2015-12-20 at 03:57 +0100, Marek Vasut wrote: > On Sunday, December 20, 2015 at 03:38:54 AM, Stefan Roese wrote: > > On 19.12.2015 17:31, Marek Vasut wrote: > > > On Saturday, December 19, 2015 at 11:03:45 AM, Stefan Roese > > > wrote: > > > > On 19.12.2015 06:58, Marek Vasut wrote: > > > > > The L2 cache was never enabled in the > > > > > v7_outer_cache_enable(), fix > > > > > this and enable the L2 cache. > > > > > > > > > > Signed-off-by: Marek Vasut <ma...@denx.de> > > > > > Cc: Dinh Nguyen <dingu...@opensource.altera.com> > > > > > Cc: Chin Liang See <cl...@altera.com> > > > > > --- > > > > > > > > > > arch/arm/mach-socfpga/misc.c | 7 +++++-- > > > > > 1 file changed, 5 insertions(+), 2 deletions(-) > > > > > > > > > > diff --git a/arch/arm/mach-socfpga/misc.c > > > > > b/arch/arm/mach-socfpga/misc.c index b110f5b..621f5d9 100644 > > > > > --- a/arch/arm/mach-socfpga/misc.c > > > > > +++ b/arch/arm/mach-socfpga/misc.c > > > > > @@ -54,14 +54,17 @@ void enable_caches(void) > > > > > > > > > > void v7_outer_cache_enable(void) > > > > > { > > > > > > > > > > - /* disable the L2 cache */ > > > > > - writel(0, &pl310->pl310_ctrl); > > > > > + /* Disable the L2 cache */ > > > > > + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); > > > > > > > > > > /* enable BRESP, instruction and data prefetch, > > > > > full line of > zeroes > > > > > */ setbits_le32(&pl310->pl310_aux_ctrl, > > > > > > > > > > L310_AUX_CTRL_DATA_PREFETCH_MASK | > > > > > L310_AUX_CTRL_INST_PREFETCH_MASK | > > > > > L310_SHARED_ATT_OVERRIDE_ENABLE); > > > > > > > > > > + > > > > > + /* Enable the L2 cache */ > > > > > + setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); > > > > > > > > Thanks Marek. I would be interested in some number here. Do you > > > > see > > > > a bigger change in the performance (ethernet driver or > > > > dhrystone) > > > > by enabling the L2 cache? > > > > > > Neither, but I didn't see any improvement on MX6 when I enabled > > > L2 > > > either. > > > > Then my feeling is, that some other configuration is needed to > > effectively enable the L2 cache on those platforms. Sorry, but > > I have no clear suggestions right now. Other than to look at > > Linux for the L2 cache enabling. > > The L2 cache is enabled, but the slowdown is not induced by the L2 > cache. > The L2 cache has no performance impact on other platforms either. Did > you > observe actual performance improvement with L2 cache ON anywhere ? >
Hmmm, here is the function for L2 cache within my development branch. Some of the latency tuning helps based on the benchmark result. Probably you can give it a try, Marek? void v7_outer_cache_enable(void) { /* disable the L2 cache */ writel(0, &pl310_regs_base->pl310_ctrl); /* enable BRESP, instruction and data prefetch, full line of zeroes */ setbits_le32(&pl310_regs_base->pl310_aux_ctrl, PL310_AUX_CTRL_FULL_LINE_ZERO_MASK | PL310_AUX_CTRL_DATA_PREFETCH_MASK | PL310_AUX_CTRL_INST_PREFETCH_MASK | PL310_AUX_CTRL_EARLY_BRESP_MASK); /* setup tag ram latency */ writel(0, &pl310_regs_base->pl310_tag_latency_ctrl); /* setup data ram latency */ writel(0x10, &pl310_regs_base->pl310_data_latency_ctrl); /* invalidate the cache before enable */ v7_outer_cache_inval_all(); /* enable the L2 cache */ writel(0x1, &pl310_regs_base->pl310_ctrl); } Thanks Chin Liang > Best regards, > Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot