Hi Bin,
On 8 December 2015 at 06:23, Bin Meng <bmeng...@gmail.com> wrote:
> Hi Simon,
>
> On Tue, Dec 1, 2015 at 12:11 PM, Simon Glass <s...@chromium.org> wrote:
>> Add a driver-model version of the pci_write_bar32 function so that this is
>> supported in the new API.
>>
>> Signed-off-by: Simon Glass <s...@chromium.org>
>> ---
>>
>> drivers/pci/pci-uclass.c | 8 ++++++++
>> include/pci.h | 11 +++++++++++
>> 2 files changed, 19 insertions(+)
>>
>> diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
>> index 77d5300..93dcb21 100644
>> --- a/drivers/pci/pci-uclass.c
>> +++ b/drivers/pci/pci-uclass.c
>> @@ -1053,6 +1053,14 @@ u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
>> return addr & PCI_BASE_ADDRESS_MEM_MASK;
>> }
>>
>> +void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr_and_ctrl)
>
> What is the ctrl bit here? Those LSb(it)s are read-only.
>
>> +{
>> + int bar;
>> +
>> + bar = PCI_BASE_ADDRESS_0 + barnum * 4;
>> + dm_pci_write_config32(dev, bar, addr_and_ctrl);
>
> And we cannot write arbitrary address here. The address to be written
> should be aligned to its bar size. We should do some sanity check
> here. Why do we need this function? Normally the BAR programming
> happens in the PCI enumeration process.
>
Some devices have hard-coded BARs. I can't be sure that this is
required but the current code needs it. Once the dust settles we can
see if there is another way.
>> +}
>> +
>> static int _dm_pci_bus_to_phys(struct udevice *ctlr,
>> pci_addr_t bus_addr, unsigned long flags,
>> unsigned long skip_mask, phys_addr_t *pa)
>> diff --git a/include/pci.h b/include/pci.h
>> index 9e811ca..f04ac99 100644
>> --- a/include/pci.h
>> +++ b/include/pci.h
>> @@ -1167,6 +1167,17 @@ int pci_get_regions(struct udevice *dev, struct
>> pci_region **iop,
>> struct pci_region **memp, struct pci_region **prefp);
>>
>> /**
>> + * dm_pci_write_bar32() - Write the address of a BAR including control bits
>> + *
>> + * This writes a raw address (with control bits) to a bar
>> + *
>> + * @dev: PCI device to update
>> + * @barnum: BAR number (0-5)
>> + * @addr: BAR address with control bits
>> + */
>> +void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr_and_ctrl);
>> +
>> +/**
>> * dm_pci_read_bar32() - read a base address register from a device
>> *
>> * @dev: Device to check
>> --
>
> Regards,
> Bin
Regards,
Simon
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