On Tue, 2015-12-15 at 19:16 +0100, Marek Vasut wrote: > On Tuesday, December 15, 2015 at 11:09:59 AM, Chin Liang See wrote: > > On Tue, 2015-12-15 at 02:15 +0100, Marek Vasut wrote: > > > On Tuesday, December 15, 2015 at 02:09:42 AM, Chin Liang See > > > wrote: > > > > On Tue, 2015-12-15 at 01:32 +0100, Marek Vasut wrote: > > > > > On Monday, December 14, 2015 at 04:22:57 PM, Chin Liang See > > > > > > > > > > wrote: > > > > > > On Mon, 2015-12-14 at 02:25 +0100, Marek Vasut wrote: > > > > > > > On Monday, December 14, 2015 at 02:22:32 AM, Chin Liang > > > > > > > See > > > > > > > > > > > wrote: > > > > [...] > > > > > > > > > > Yeah, I can successfully mounted with ubifs :) > > > > > > > > > > > > Just that I still have the issue with U-Boot ubifsmount > > > > > > although I > > > > > > already applied the patch for cache ARMV7. I will take a > > > > > > look > > > > > > into > > > > > > ubi > > > > > > code as I suspect its due to eraseblock size issue. > > > > > > > > > > Keep looking, good luck. > > > > > > > > Yup, will compare the UBI code with the Linux one. > > > > Yeah, I managed to get ubiufsmount work in U-Boot now. Need to > > disable > > the 4K_SECTORS when enabling UBI at NOR flash. > > In that case, look at commit 0a02655481834a4ebdf457e43c24729ffd7daf37
Yup, I was defining that macro. Surprising that nobody is defining that. Also nice to know you are the one creating this patch. > > > > > > The armv7 cache issue is more serious than I thought, I am > > > > > starting > > > > > to suspect > > > > > there is some problem with the L3 interconnect, but I cannot > > > > > put > > > > > my > > > > > finger on > > > > > it yet. > > > > > > > > Hmmm... I can try to help. > > > > > > > > FYI, I was trying to understand how the code error in cache > > > > -cp15 > > > > will > > > > cause the misbehave. One thing I am suspecting it might due to > > > > mismatch > > > > of cache policy for the memory that store the page table and > > > > translation page walk mechanism. But with your fix, it should > > > > be > > > > good > > > > as they are matching now. > > > > > > I would suggest to move this to the thread below the CPU_V7 > > > patch. > > > > Would you able to include me to the thread? Thanks in advance! > > https://www.mail-archive.com/u-boot@lists.denx.de/msg195327.html > > > > btw. the L2 cache is not enabled on SoCFPGA at all :-( I have a > > > patch > > > to fix > > > it, but this doesn't help us. > > > > Hmmm... I saw the PL310 is defined. I might want to look further. > > I will send that patch out shortly, but I think there is something > else > going on. I am starting to suspect something with the L3 > interconnect. > Maybe some R/W reordering or something like that in NIC301 . > > Are you able to replicate my USB issue with mainline on socfpga ? > What > happens if you run usb reset with a USB stick plugged in? What > compiler > version do you use ? I tried that few weeks back and it works for me. FYI, I am using the mentor toolchain "arm-altera-eabi" that come with SOCEDS. Maybe I can try again with your toolchain. Thanks Chin Liang > > > > I suspect there might be some synchronisation > > > or timing issue with accesses through the L3 interconnect, which > > > would point > > > to NIC301 misconfiguration, but that's purely hypothetical.Do you > > > have some > > > hardware-level or RTL-level/simulation tool to debug such issues > > > at > > > Altera ? > > > > I hardly use simulation except for in house pre-silicon validation. > > But > > I use DS-5 a lot to troubleshoot an issue (by probing various > > registers > > including cp15). > > > > Thanks > > Chin Liang > > > > > Best regards, > > > Marek Vasut > > Best regards, > Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
