On Wednesday, December 02, 2015 at 08:31:28 PM, dingu...@opensource.altera.com
wrote:
> From: Dinh Nguyen <dinh.li...@gmail.com>
>
> Add arch_early_init_r function. The Arria10 has a firewall protection
> around the SDRAM and OCRAM. These firewalls are to be disabled in order
> for U-Boot to function.
>
> Signed-off-by: Dinh Nguyen <dingu...@opensource.altera.com>
> ---
> v4: be consistent and use #if->else throughout
> v3:
> s/reset_assert_all_peripherals_except_l4wd0_l4timer0/socfpga_per_reset_all
> use CONFIG_SOCFPGA_GEN5
> v2: reuse misc functions from a5/c5
> ---
> arch/arm/mach-socfpga/misc.c | 51
> ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51
> insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> index b110f5b..78774d5 100644
> --- a/arch/arm/mach-socfpga/misc.c
> +++ b/arch/arm/mach-socfpga/misc.c
> @@ -15,6 +15,7 @@
> #include <watchdog.h>
> #include <asm/arch/reset_manager.h>
> #include <asm/arch/scan_manager.h>
> +#include <asm/arch/sdram_a10.h>
> #include <asm/arch/system_manager.h>
> #include <asm/arch/dwmmc.h>
> #include <asm/arch/nic301.h>
> @@ -31,8 +32,15 @@ static struct socfpga_system_manager *sysmgr_regs =
> (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> static struct socfpga_reset_manager *reset_manager_base =
> (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> static struct nic301_registers *nic301_regs =
> (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
> +#else
> +static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
> + (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
> +static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =
> + (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
> +#endif
> static struct scu_registers *scu_regs =
> (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
>
> @@ -207,9 +215,14 @@ static int socfpga_fpga_id(const bool print_id)
> #if defined(CONFIG_DISPLAY_CPUINFO)
> int print_cpuinfo(void)
> {
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
> puts("CPU: Altera SoCFPGA Platform\n");
> socfpga_fpga_id(1);
> +#else
> + const u32 bsel = (readl(&sysmgr_regs->bootinfo) >> 12) & 0x7;
Is the bsel meaning the same for both Gen5 and Gen10 ? If so, that's fine.
You can improve this code here by defining some bootinfo offset, 0 for gen5
and 12 for gen10 and then you'd only need to ifdef the puts() and the invocation
of socfpga_fpga_id();
Can you send a subsequent patch for this ?
> + puts("CPU: Altera SoCFPGA Arria 10\n");
> +#endif
> printf("BOOT: %s\n", bsel_str[bsel].name);
> return 0;
> }
> @@ -292,6 +305,7 @@ int arch_cpu_init(void)
Anyway, let me just apply this.
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