For 36-bit addressing mode, PCIe virtual memory addresses have been
different from PCI bus addresses. This causes confusion when trying
to access the PCI address manually. Previously it was believed
overlapping PCI(e) controllers' space would leave more room for large
memory. Actually u-boot has been using no more than 512MB for each
controller. Making the bus address same as virtual address simplifies
the address space, and users can access PCI(e) space under u-boot
prompt without calcuating the offset.
No change for 32-bit mode as the addresses are consistent.
Signed-off-by: York Sun <york...@freescale.com>
---
Tested on P4080DS, P1022DS, T2080QDS.
include/configs/B4860QDS.h | 3 +--
include/configs/MPC8536DS.h | 12 ++++--------
include/configs/MPC8548CDS.h | 6 ++----
include/configs/MPC8572DS.h | 9 +++------
include/configs/MPC8641HPCN.h | 12 +-----------
include/configs/P1010RDB.h | 6 ++----
include/configs/P1022DS.h | 9 +++------
include/configs/P2041RDB.h | 9 +++------
include/configs/T102xQDS.h | 9 +++------
include/configs/T102xRDB.h | 12 ++++--------
include/configs/T1040QDS.h | 8 ++++----
include/configs/T104xRDB.h | 8 ++++----
include/configs/T208xQDS.h | 8 ++++----
include/configs/T208xRDB.h | 8 ++++----
include/configs/T4240RDB.h | 9 +++++----
include/configs/controlcenterd.h | 3 +--
include/configs/corenet_ds.h | 12 +++++-------
include/configs/cyrus.h | 12 +++++-------
include/configs/km/kmp204x-common.h | 4 ++--
include/configs/p1_p2_rdb_pc.h | 6 ++----
include/configs/t4qds.h | 6 +++---
21 files changed, 65 insertions(+), 106 deletions(-)
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index c83e5ce..66ead35 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -609,11 +609,10 @@ unsigned long get_board_ddr_clk(void);
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 29c27fa..51d69c5 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -435,11 +435,10 @@
*/
#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
#else
-#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
#endif
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
@@ -455,11 +454,10 @@
/* controller 1, Slot 1, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_NAME "Slot 1"
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
+#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
@@ -475,11 +473,10 @@
/* controller 2, Slot 2, tgtid 2, Base address 9000 */
#define CONFIG_SYS_PCIE2_NAME "Slot 2"
#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
+#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
#endif
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
@@ -495,11 +492,10 @@
/* controller 3, direct to uli, tgtid 3, Base address 8000 */
#define CONFIG_SYS_PCIE3_NAME "Slot 3"
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
#endif
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 517b449..eed97b1 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -362,11 +362,10 @@ extern unsigned long get_clock_freq(void);
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
#else
-#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
#endif
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
@@ -382,11 +381,10 @@ extern unsigned long get_clock_freq(void);
#ifdef CONFIG_PCIE1
#define CONFIG_SYS_PCIE1_NAME "Slot"
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 19da477..afe96fc 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -423,11 +423,10 @@
/* controller 3, direct to uli, tgtid 3, Base address 8000 */
#define CONFIG_SYS_PCIE3_NAME "ULI"
#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
#endif
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
@@ -443,11 +442,10 @@
/* controller 2, Slot 2, tgtid 2, Base address 9000 */
#define CONFIG_SYS_PCIE2_NAME "Slot 1"
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
#endif
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
@@ -463,11 +461,10 @@
/* controller 1, Slot 1, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_NAME "Slot 2"
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 6f1535e..c088b92 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -313,12 +313,11 @@ extern unsigned long get_board_sys_clk(unsigned long
dummy);
#define CONFIG_SYS_PCIE1_NAME "ULI"
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000
#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c
#else
-#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT
#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000
#endif
@@ -334,17 +333,8 @@ extern unsigned long get_board_sys_clk(unsigned long
dummy);
CONFIG_SYS_PHYS_ADDR_HIGH)
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */
-#ifdef CONFIG_PHYS_64BIT
-/*
- * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
- * This will increase the amount of PCI address space available for
- * for mapping RAM.
- */
-#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS
-#else
#define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \
+ CONFIG_SYS_PCIE1_MEM_SIZE)
-#endif
#define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \
+ CONFIG_SYS_PCIE1_MEM_SIZE)
#define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 81b0855..24b8146 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -193,11 +193,10 @@
/* controller 1, Slot 1, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot"
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
@@ -217,11 +216,10 @@
#define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot"
#endif
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
#endif
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index a9d825b..5d31712 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -494,11 +494,10 @@
/* controller 1, Slot 2, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
@@ -513,11 +512,10 @@
/* controller 2, direct to uli, tgtid 2, Base address 9000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
#endif
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
@@ -532,11 +530,10 @@
/* controller 3, Slot 1, tgtid 3, Base address b000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
#endif
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 2c4c8b5..d9c7677 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -423,11 +423,10 @@ unsigned long get_board_sys_clk(unsigned long dummy);
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
@@ -442,11 +441,10 @@ unsigned long get_board_sys_clk(unsigned long dummy);
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
#endif
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
@@ -461,11 +459,10 @@ unsigned long get_board_sys_clk(unsigned long dummy);
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
#endif
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index 52942ed..15ec054 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -606,11 +606,10 @@ unsigned long get_board_ddr_clk(void);
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#ifdef CONFIG_PCIE1
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
@@ -627,11 +626,10 @@ unsigned long get_board_ddr_clk(void);
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#ifdef CONFIG_PCIE2
#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
+#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
#endif
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
@@ -648,11 +646,10 @@ unsigned long get_board_ddr_clk(void);
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#ifdef CONFIG_PCIE3
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
#endif
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 39fa5e2..65f7e4c 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -598,11 +598,10 @@ unsigned long get_board_ddr_clk(void);
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#ifdef CONFIG_PCIE1
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
@@ -619,11 +618,10 @@ unsigned long get_board_ddr_clk(void);
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#ifdef CONFIG_PCIE2
#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
+#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
#endif
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
@@ -640,11 +638,10 @@ unsigned long get_board_ddr_clk(void);
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#ifdef CONFIG_PCIE3
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
#endif
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
@@ -661,11 +658,10 @@ unsigned long get_board_ddr_clk(void);
/* controller 4, Base address 203000, to be removed */
#ifdef CONFIG_PCIE4
#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS CONFIG_SYS_PCIE4_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
#else
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000
#endif
#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index fc263df..e4e410c 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -500,7 +500,7 @@ unsigned long get_board_ddr_clk(void);
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#ifdef CONFIG_PCIE1
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
@@ -512,7 +512,7 @@ unsigned long get_board_ddr_clk(void);
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#ifdef CONFIG_PCIE2
#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
@@ -524,7 +524,7 @@ unsigned long get_board_ddr_clk(void);
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#ifdef CONFIG_PCIE3
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
@@ -536,7 +536,7 @@ unsigned long get_board_ddr_clk(void);
/* controller 4, Base address 203000 */
#ifdef CONFIG_PCIE4
#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS CONFIG_SYS_PCIE4_MEM_VIRT
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 840be04..918c72a 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -558,7 +558,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#ifdef CONFIG_PCIE1
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
@@ -570,7 +570,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#ifdef CONFIG_PCIE2
#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
@@ -582,7 +582,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#ifdef CONFIG_PCIE3
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
@@ -594,7 +594,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
/* controller 4, Base address 203000 */
#ifdef CONFIG_PCIE4
#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS CONFIG_SYS_PCIE4_MEM_VIRT
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index a81f1e6..0d71568 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -578,7 +578,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
@@ -588,7 +588,7 @@ unsigned long get_board_ddr_clk(void);
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
@@ -598,7 +598,7 @@ unsigned long get_board_ddr_clk(void);
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
@@ -608,7 +608,7 @@ unsigned long get_board_ddr_clk(void);
/* controller 4, Base address 203000 */
#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS CONFIG_SYS_PCIE4_MEM_VIRT
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 8b76234..b86e353 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -526,7 +526,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
@@ -536,7 +536,7 @@ unsigned long get_board_ddr_clk(void);
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
@@ -546,7 +546,7 @@ unsigned long get_board_ddr_clk(void);
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
@@ -556,7 +556,7 @@ unsigned long get_board_ddr_clk(void);
/* controller 4, Base address 203000 */
#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS CONFIG_SYS_PCIE4_MEM_VIRT
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 2e875d2..1ad2029 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -238,7 +238,7 @@
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
@@ -248,7 +248,7 @@
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
@@ -258,7 +258,7 @@
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
@@ -267,7 +267,8 @@
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS (CONFIG_SYS_PCIE3_MEM_BUS +\
+ CONFIG_SYS_PCIE3_MEM_SIZE)
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index 600bb83..4ed987b 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -266,11 +266,10 @@
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 9210216..77a8d62 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -428,11 +428,10 @@
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
@@ -447,11 +446,10 @@
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
#endif
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
@@ -466,11 +464,10 @@
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
#endif
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
@@ -484,7 +481,8 @@
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS (CONFIG_SYS_PCIE3_MEM_BUS +\
+ CONFIG_SYS_PCIE3_MEM_SIZE)
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index 5d25fb1..7a87c7e 100644
--- a/include/configs/cyrus.h
+++ b/include/configs/cyrus.h
@@ -289,11 +289,10 @@
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
@@ -308,11 +307,10 @@
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
#endif
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
@@ -327,11 +325,10 @@
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
#endif
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
@@ -345,7 +342,8 @@
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS (CONFIG_SYS_PCIE3_MEM_BUS +\
+ CONFIG_SYS_PCIE3_MEM_SIZE)
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
diff --git a/include/configs/km/kmp204x-common.h
b/include/configs/km/kmp204x-common.h
index e163edb..342536f 100644
--- a/include/configs/km/kmp204x-common.h
+++ b/include/configs/km/kmp204x-common.h
@@ -312,7 +312,7 @@ int get_scl(void);
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
@@ -322,7 +322,7 @@ int get_scl(void);
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 433c409..cce7db1 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -728,11 +728,10 @@
/* controller 2, direct to uli, tgtid 2, Base address 9000 */
#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
#endif
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
@@ -748,11 +747,10 @@
/* controller 1, Slot 2, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index 5754369..0a7ccf6 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -193,7 +193,7 @@
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
@@ -203,7 +203,7 @@
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
@@ -213,7 +213,7 @@
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
--
1.7.9.5
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