On Thursday, November 19, 2015 at 10:35:42 PM, dingu...@opensource.altera.com
wrote:
> From: Dinh Nguyen <dingu...@opensource.altera.com>
>
> Add miscellaneous functions(arch_early_init_r, print_cpuinfo,
> overwrite_console, enable_caches, and cpu_mmc_init). Also, the Arria10
> has a firewall protection around the SDRAM and OCRAM. These firewalls
> are to be disabled in order for U-Boot to function.
>
> Signed-off-by: Dinh Nguyen <dingu...@opensource.altera.com>
> ---
Hi!
[..]
> +/* FPGA programming support for SoC FPGA Arria 10 */
> +static Altera_desc altera_fpga[] = {
> + {
> + /* Family */
> + Altera_SoCFPGA,
> + /* Interface type */
> + fast_passive_parallel,
> + /* No limitation as additional data will be ignored */
> + -1,
> + /* No device function table */
> + NULL,
> + /* Base interface address specified in driver */
> + NULL,
> + /* No cookie implementation */
> + 0
> + },
> +};
Looks like AV/CV misc.c , so we should definitelly make this into common code.
> +/* add device descriptor to FPGA device table */
> +static void socfpga_fpga_add(void)
> +{
> + int i;
> + fpga_init();
> + for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
> + fpga_add(fpga_altera, &altera_fpga[i]);
> +}
> +
> +void v7_outer_cache_enable(void)
> +{
> + /* disable the L2 cache */
> + writel(0, &pl310_regs_base->pl310_ctrl);
> +
> + /* enable BRESP, instruction and data prefetch, full line of zeroes */
> + setbits_le32(&pl310_regs_base->pl310_aux_ctrl,
> + L310_AUX_CTRL_DATA_PREFETCH_MASK |
> + L310_AUX_CTRL_INST_PREFETCH_MASK);
> +}
[...]
> +#ifdef CONFIG_DWMMC
> +/*
> + * Initializes MMC controllers.
> + * to override, implement board_mmc_init()
> + */
> +int cpu_mmc_init(bd_t *bis)
> +{
> + return socfpga_dwmmc_init(gd->fdt_blob);
> +}
> +#endif
This part needs fixing for Cyclone V / Arria V and also for Arria 10. The DWMMC
should probe from DT automatically and this bit should not be needed at all. The
socfpga_dwmmc_init() function should also be removed from the socfpga dwmmc shim
in drivers/mmc/ .
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