On Thursday, November 19, 2015 at 10:35:40 PM, dingu...@opensource.altera.com wrote: > From: Dinh Nguyen <dingu...@opensource.altera.com> > > Add the defines for the reset manager and some basic reset functionality. > > Signed-off-by: Dinh Nguyen <dingu...@opensource.altera.com> > --- > arch/arm/mach-socfpga/arria10/reset_manager_a10.c | 83 +++++++++++ > .../mach-socfpga/include/mach/reset_manager_a10.h | 162 > +++++++++++++++++++++ 2 files changed, 245 insertions(+) > create mode 100644 arch/arm/mach-socfpga/arria10/reset_manager_a10.c > create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_a10.h > > diff --git a/arch/arm/mach-socfpga/arria10/reset_manager_a10.c > b/arch/arm/mach-socfpga/arria10/reset_manager_a10.c new file mode 100644 > index 0000000..e2d315a > --- /dev/null > +++ b/arch/arm/mach-socfpga/arria10/reset_manager_a10.c > @@ -0,0 +1,83 @@ > +/* > + * Copyright (C) 2014 Altera Corporation <www.altera.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <asm/io.h> > +#include <asm/arch/reset_manager_a10.h> > +#include <asm/arch/system_manager_a10.h> > +#include <fdtdec.h> > + > +DECLARE_GLOBAL_DATA_PTR;
This whole file looks pretty similar to the CV/AV reset manager, can't we just merge those two into a single file ? btw. I dont think you need the DECLARE_GLOBAL_DATA_PTR here. > +static const struct socfpga_reset_manager *reset_manager_base = > + (void *)SOCFPGA_RSTMGR_ADDRESS; > + [...] > +#define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK 0x00000001 > +#define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK 0x00000002 > +#define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK 0x00000004 > +#define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK 0x00000008 > +#define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK 0x00000010 > +#define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK 0x00000020 > +#define ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK 0x00000040 All these are probably just bits, so please use 1 << n here. > +#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET_MSK 0x00000001 > +#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET_MSK 0x00000002 > +#define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK 0x00000004 > +#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK 0x00000008 > + > +/* > + * Define a reset identifier, from which a permodrst bank ID > + * and reset ID can be extracted using the subsequent macros > + * RSTMGR_RESET() and RSTMGR_BANK(). > + */ > +#define RSTMGR_BANK_OFFSET 8 > +#define RSTMGR_BANK_MASK 0x7 > +#define RSTMGR_RESET_OFFSET 0 > +#define RSTMGR_RESET_MASK 0x1f > +#define RSTMGR_DEFINE(_bank, _offset) \ > + ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET) > + > +/* Extract reset ID from the reset identifier. */ > +#define RSTMGR_RESET(_reset) \ > + (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK) > + > +/* Extract bank ID from the reset identifier. */ > +#define RSTMGR_BANK(_reset) \ > +(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK) > + > +/* > + * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows: Oh yeah ? Looks arria10-ish to me :-) > + * 0 ... mpumodrst > + * 1 ... per0modrst > + * 2 ... per1modrst > + * 3 ... brgmodrst > + * 4 ... sysmodrst > + */ > +#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) > +#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) > +#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2) > +#define RSTMGR_WD0 RSTMGR_DEFINE(2, 0) > +#define RSTMGR_WD1 RSTMGR_DEFINE(2, 1) > +#define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2) > +#define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3) > +#define RSTMGR_SPTIMER0 RSTMGR_DEFINE(2, 4) > +#define RSTMGR_SPTIMER1 RSTMGR_DEFINE(2, 5) > +#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16) > +#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17) > +#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17) > +#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18) > +#define RSTMGR_QSPI RSTMGR_DEFINE(1, 6) > +#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7) > +#define RSTMGR_DMA RSTMGR_DEFINE(1, 16) > +#define RSTMGR_DDRSCH RSTMGR_DEFINE(3, 6) > + > +/* Create a human-readable reference to SoCFPGA reset. */ > +#define SOCFPGA_RESET(_name) RSTMGR_##_name > + > +#endif /* _SOCFPGA_RESET_MANAGER_A10_H_ */ _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
